Fujitsu MB96300 series Hardware Manual page 417

MB96300 Super Series Hardware Manual
■ Reload Timer Input Select Register (TMISR)
Figure 15.7-2
7 6 5
- - TMS5
- - R/W
R/W : Readable and writable
W : Write only
X : undefined value
- : undefined
: Initial value
■ Description of operation
The first Reload Timer in the chain can either have an internal clock or an external event as counter clock. It
can be configured freely.
The next Reload Timer and all following in the chain must be set as follows:
• TMCSRn:MOD[2:0] = "101" : Gate count mode "H" level
• TMCSRn:CSL[1:0] = "00" and TMCSRn:FSEL = "1" : CLKP1 is divided by 2 (cf table 16.2-1) but all
RLT, except the first RLT, are clocked with CLKP1 divided by 2 to make sure that the UF signal, which
is CLKP1 period long, is sampled.
• TMISR:TMISx = "1" : Use underflow signal of preceding timer as count enable signal
All Reload Timers must be triggered before counting starts to load the reload value and to change the Reload
timers to RUN-State (see Figure 15.6-1 "Counter state transitions").
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT
Reload Timer Input Select Register (TMISR)
4 3 2 1 0
TMS4 TMS3 TMS2 TMS1 TMS0
R/W R/W R/W R/W R/W
TMISR
Initial value
X X 0 0 0 0 0 0
B
bit0
TMIS0 Reload Timer 0 Input Select
0
use TIN0 as trigger input
1
use Underflow event of Reload Timer 5 as trigger input
bit1
TMIS1 Reload Timer 1 Input Select
0
use TIN1 as trigger input
1
use Underflow event of Reload Timer 0 as trigger input
bit2
TMIS2 Reload Timer 2 Input Select
0
use TIN2 as trigger input
1
use Underflow event of Reload Timer 1 as trigger input
bit3
TMIS3 Reload Timer 3 Input Select
0
use TIN3 as trigger input
1
use Underflow event of Reload Timer 2 as trigger input
bit4
TMIS4 Reload Timer 4 Input Select
0
use TIN4 as trigger input
1
use Underflow event of Reload Timer 3 as trigger input
bit5
TMIS5 Reload Timer 5 Input Select
0 use TIN5 as trigger input
1
use Underflow event of Reload Timer 4 as trigger input
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