Fujitsu MB96300 series Hardware Manual page 670

F2mc-16fx 16-bit
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CHAPTER 25 CLOCK CALIBRATION UNIT
new calibration. Otherwise the end of the calibration process is only signalized by the STRT bit (the INT
flag stays 1 also during calibration).
BIT[2]: CKSEL - Input clock select
0
use CLKSC (default)
1
use CLKRC
The RC-clock frequency depends on the setting of CKSCR:RCFS bit (RC-Oscillator frequency select).
Devices with sub clock: If the Clock setting shall be changed, the clock which is currently selected must
be active for at lease 3 cycles if it was enabled at any time before. Otherwise the selected clock does not
change to the new clock.
BIT[4]: STRT - Calibration Start
0
calibration stopped, module switched off (default)
1
start calibration
When the STRT bit is set to 1 by the software, the calibration starts. The Duration Timer starts counting
down from the value stored in the Duration Timer Data Register CUTD and the Calibration starts
counting up from zero.
When the Duration Timer reaches zero, this bit is reset to 0 by the hardware.
If 0 is written into this bit by the software during the calibration process, the calibration is immediately
stopped. If writing 0 by the software and reset to 0 by the hardware happens at the same time, the
hardware operation supersede the software operation. This means the calibration is properly completed
and the INT bit is set to "1". Writing 1 to this bit during the calibration has no effect.
BIT[7]: RES - Reserved bit
Always write "0". The read value is undefined. Read-modify-write is not affected.
■ Clock Calibration Unit Duration Timer Data Register (CUTD)
Duration Timer Register high byte
Duration Timer Register low byte
The Clock Calibration Unit Duration Timer Data Register (CUTD) holds the value which determines the
duration of calibration, i. e. it stores Duration Timer reload value.When the calibration is started, the stored
value is loaded into the Low Speed Timer and the timer starts counting down until it reaches zero.
The Clock Calibration Unit Duration Timer operates with CLKSC or with CLKRC clock, depending on the
setting of CUCR:CKSEL.
Default value is 0x8000 which corresponds to a measurement duration of 1 second, if CLKSC is used with a
32.768 kHz crystal.
This register should be written only when the calibration is inactive (STRT=0).
662
15
14
TDD15TDD14 TDD13 TDD12 TDD11TDD10
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(0)
Default value⇒
7
6
TDD7 TDD6 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Default value⇒
MB96300 Super Series Hardware Manual
13
12
11
10
9
TDD9 TDD8
(0)
(0)
(0)
(0)
(0)
5
4
3
2
(0)
(0)
(0)
(0)
(0)
⇐ Bit no.
8
CUTDH
(0)
⇐ Bit no.
1
0
CUTDL
(0)

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