Fujitsu MB96300 series Hardware Manual page 229

MB96300 Super Series Hardware Manual
Table 8.6-1 Clock stop detection interval
Observed
clock
Sub clock
The minimum time specifies after which time between two rising edges of the observed clock a stop
detection may occur. The maximum time specifies after which time a clock stop will be detected. Use a
setting with a minimum time that is longer than the cycle time of the observed clock (the observed clock
frequency must be higher than the minimum external frequency given in Table 8.6-1).
Changing the RC clock frequency during operation of the clock stop detect function is allowed but changes
the detection interval.
■ Clock missing flags MCMF and SCMF
The Main Clock Missing Flag MCMF indicates a missing Main clock and the Sub Clock Missing Flag
SCMF indicates a missing Sub clock.
●
Status after power-on
The clock missing flags MCMF and SCMF are undefined after startup.
●
Clearing the clock missing flags
The MCMF and SCMF bits can be cleared by a read access to the RCCSRC register at address 00040B
●
Setting the clock missing flags
The Main clock stop detection circuit is enabled when the RC clock is running and the Main oscillator is
active (active means the Main Clock Enable bit CKSR: MCE is "1" or the Main Clock Monitor bit CKMR:
MCM is "1"). The Main Clock Missing Flag is set to "1" when no rising edge of the Main clock input signal
was detected within the selected interval.
The Sub clock stop detection circuit is enabled when the RC clock is running and the Sub oscillator is active
(active means the Sub Clock Enable bit CKSR: SCE is "1" or the Sub Clock Monitor bit CKMR: SCM is
"1"). The Sub Clock Missing Flag is set to "1" when no rising edge of the Sub clock input signal was
detected within the selected interval.
■ Clock stop detection reset
The Clock stop detection reset function generates a reset if a clock failure is detected while this clock is used
as source for the System clocks (CLKS1 or CLKS2) or the Watchdog timer.
Select
Setting
bit
0 (initial value)
SCSDI
1
CHAPTER 8 RESETS AND STARTUP
Clock Stop Detection Interval
RC clock Time for RC clock
cycles frequency of
2MHz (min - max) /
(minimum
external
frequency)
96µs - 512µs /
384 - 512
(~11kHz)
24 - 32 6µs - 32µs /
(~170kHz)
Time for RC clock
frequency of
100kHz (min - max)
/ (minimum
external
frequency)
1.92ms - 10.2ms /
(~0.55kHz)
12µs - 640µs /
(~8.5kHz)
.
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