Fujitsu MB96300 series Hardware Manual page 400

CHAPTER 14 16-BIT I/O TIMER
Figure 14.5-4 Input Capture Unit Edge Register (ICE(2n)(2n+1))
X : undefined value
R/W : readable and writable
Table 14.5-3 Input Capture Unit Edge Register bits (upper and lower)
Bit name
bit15 to 10 RES
bit9 IEI(2n+1):
Valid edge
indication bit
bit8 IEI(2n):
Valid edge
indication bit
The suffix n = 0, 1, 2, 3, ... denotes the Input Capture Unit number. The bit names are composed by their type name and the
suffix. Hence, for
n = 0: IEI1, IEI0
n = 1: IEI3, IEI2 etc.
392
15 14 13 12 11 10 9
RES RES RES RES RES RES IEI(2n+1)IEI(2n)
- - - - - - R/W R/W
Some bits contain device specific configuration bits. For details, see 1.6 "Input
Capture Unit source select for LIN-USART"
• This bit is the edge indication bit for capture register IPCP(2n+1) to indicate that
a rising or falling edge is detected.
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note: The read value is meaningless, if EG(2n+1)1, EG(2n+1)0 = "00".
The read value is independent from edge selected by EG(2n+1)1 and EG(2n+1)0
• This bit is the edge indication bit for capture register IPCP0, IPCP2, IPCP4 and
IPCP6 to indicate that a rising or falling edge is detected
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note: The read value is meaningless, if EG(2n)1, EG(2n)0 = "00".
The read value is independent from edge selected by EG(2n)1 and EG(2n)0
MB96300 Super Series Hardware Manual
8
ICE(2n)(2n+1)
.
.
bit8
IEI(2n)
Input capture valid edge indication bit for ICU0
0
falling edge detected
1
rising edge detected
bit9
IEI(2n+1)
Input capture valid edge indication bit for ICU1
0
falling edge detected
1
rising edge detected
bit10-15
-
Some bits contain device specific configuration bits.
For details, see Chapter 1. For other bits:
read value is undefined, write always 0
read modify instructions are not affected
Function
Initial value
X X X X X X 0 0
B
reserved bit
n = 0, 1, 2, 3,...