Fujitsu MB96300 series Hardware Manual page 934

APPENDIX
Table A-1 I/O map of MB96V300 (16/50)
Address
0003DCH Memory Patch function - Patch data 6
0003DDH Memory Patch function - Patch data 6
0003DEH Memory Patch function - Patch data 7
0003DFH Memory Patch function - Patch data 7
0003F1H Flash Memory Configuration register (Main Flash) +
EVA
0003F2H Flash Memory Timing Configuration register 0 (Main
Flash) + EVA
0003F3H Flash Memory Timing Configuration register 1 (Main
Flash)
0003F5H Flash Memory Configuration register (Sat Flash)
0003F6H Flash Memory Timing Configuration register 0 (Sat
Flash) + EVA
0003F7H Flash Memory Timing Configuration register 1 (Sat
Flash)
0003F8H Flash Memory Write Control register 0
0003F9H Flash Memory Write Control register 1
0003FAH Flash Memory Write Control register 2
0003FBH Flash Memory Write Control register 3
0003FCH Flash Memory Write Control register 4
0003FDH Flash Memory Write Control register 5
000400H Standby Mode control register
000401H Clock select register
000402H Clock Stabilisation select register
000403H Clock monitor register
000404H Clock Frequncy control register Low
000405H Clock Frequncy control register High
000406H PLL Control register Low
000407H PLL Control register High
000408H RC clock timer control register
000409H Main clock timer control register
00040AH Sub clock timer control register
926
Register
MB96300 Super Series Hardware Manual
Abbreviation Abbreviation
8-bit access 16-bit access
PFDL6 PFD6
PFDH6
PFDL7 PFD7
PFDH7
MFMCS
MFMTCL MFMTC
MFMTCH
SFMCS
SFMTCL SFMTC
SFMTCH
FMWC0
FMWC1
FMWC2
FMWC3
FMWC4
FMWC5
SMCR
CKSR
CKSSR
CKMR
CKFCRL CKFCR
CKFCRH
PLLCRL PLLCR
PLLCRH
RCTCR
MCTCR
SCTCR
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW