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MB96300 Super Series Hardware Manual
■ Block Diagram
CLKMC
gate
STRT
READY
RUNS
CLKSC
gate
CLKRC
STRT
CLKP1
gate
RSLEEPB
gate
RSLEEPB
STRT
CLKPG2 = CLKP1 | (~STRT & RSLEEPB);
STRT
RB
RSLEEP
RMW
INT
*_RD
*_WR
RST
Figure 25.1-1 Block Diagram
CLK
CLKMCG = CLKMC | ~STRT | (READY & ~RUNS);
CLKPG
Duration Timer (CLKSC/CLKRC) TRD
CLKSRCG
CLKPG2
CUTD
counter (16 bit)
STRTS
&
sync
STRT
CLKP1->
CLKSC/CLKRC
async
RST
STRT
RB
BUS
RBB
RSLEEPB
RMWB
IO
INT_I
*_RDB
*_WRB
RSTB
CHAPTER 25 CLOCK CALIBRATION UNIT
CLKMCG
RUN
sync
CLKSC/CLKRC
async
-> CLKMC
RUN
RST
READY
READY
reset
STRT
set / reset
INTEN
set / reset
set
INT
READYPULSE
reset
CUCR (3 bit)
&
INT_INT
CUTR (24 bit)
CUTD (16 bit)
Calibration Timer (CLKMC)
CUTR (24 bit)
RUNS
TRR
RBI
READY
RUNSS1
&
sync
RUNSS
CLKMC->CLKP1
CUTD
CUTR
659
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