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MB96300 Super Series Hardware Manual
■ Handling of Interrupts
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the
highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has
cleared it.
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object's interrupt
priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object's INTPND bit. The Status Interrupt is cleared
by reading the Status Register.
The interrupt identifier INTID in the Interrupt Register INTRn indicates the cause of the interrupt. When no
interrupt is pending, the register will hold the value zero. If the value of the Interrupt Register is different
from zero, then there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active. The
interrupt line remains active until the Interrupt Register is back to value zero (the cause of the interrupt is
reset) or until IE is reset.
The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily
changed) the Status Register (Error Interrupt or Status Interrupt). This interrupt has the highest priority. The
CPU can update (reset) the status bits RXOK, TXOK and LEC, but a write access of the CPU to the Status
Register can never generate or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects, INTID points to the
pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE and SIE in the
CAN Control Register) and whether the interrupt line becomes active when the Interrupt Register is different
from zero (bit IE in the CAN Control Register). The Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt. First it can follow the INTID in
the Interrupt Register and second it can poll the Interrupt Pending Register (see section 22.8 "Message
Handler Registers").
An interrupt service routine reading the message that is the source of the interrupt may read the message and
reset the Message Object's INTPND at the same time (bit CIP in the Command Mask Register IFxCMSKn).
When INTPND is cleared, the Interrupt Register will point to the next Message Object with a pending
interrupt.
■ Bit Time and Bit Rate
CAN supports bit rates in the range of lower than 1kBit/s up to 1000kBit/s. Each member of the CAN
network has its own clock generator, usually a quartz oscillator. The timing parameter of the bit time (i.e. the
reciprocal of the bit rate) can be configured individually for each CAN node, creating a common bit rate even
though the CAN nodes' oscillator periods (fosc) may be different.
The frequencies of these oscillators are not absolutely stable, small variations are caused by changes in
temperature or voltage and by deteriorating components. As long as the variations remain inside a specific
oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by
resynchronising to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure 22.9-5 "Bit
Timing"). The Synchronisation Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and
the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see
Table 1). The length of the time quantum (tq) , which is the basic time unit of the bit time, is defined by the
CAN controller's system clock fsys and the Baud Rate Prescaler (BRP) : tq = BRP / fsys. The CAN's system
clock fsys is the frequency of its CAN_CLK input.
CHAPTER 22 CAN CONTROLLER
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