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MB96300 Super Series Hardware Manual
Figure 10.4-2 Configuration of the Sub Clock Timer Control Register (SCTCR)
7
Address:
00040A
-
SCTIE SCTIF SCTR
H
-
R/W R/W
X
: undefined value
W
: Write only (read always returns "1")
R/W
: Readable and writable
: Initial value
6
5
4
3
2
1
0
SCTI2 SCTI1 SCTI0
-
W
-
R/W R/W R/W
CHAPTER 10 SOURCE CLOCK TIMERS
Initial value
X 0 0 1 X 0 0 0
B
bit2
bit1
bit0
Sub Clock Timer Interrupt interval
(The corresponding time for a Sub clock
SCTI2
SCTI1
SCTI0
of 32.768kHz is given in parentheses)
10
0
0
0
2
/ CLKSC (31.25 ms)
11
0
0
1
2
/ CLKSC (62.5 ms)
12
0
1
0
2
/ CLKSC (125 ms)
13
0
1
1
2
/ CLKSC (250 ms)
14
1
0
0
2
/ CLKSC (500 ms)
15
1
0
1
2
/ CLKSC (1 s)
16
1
1
0
2
/ CLKSC (2 s)
17
1
1
1
2
/ CLKSC (4 s)
bit3
-
Reserved
0
Always write "0" to this bit
bit4
Sub Clock Timer Reset bit
SCTR
Read
0
always reads 1
1
bit5
Sub Clock Timer Interrupt Flag
SCTIF
Read
0
no interrupt
1
interrupt requested
bit6
SCTIE
Sub Clock Timer Interrupt Enable bit
0
Disable Interrupt
1
Enable Interrupt
bit7
-
Reserved
0
Always write "0" to this bit
Write
reset all bits to 0
no effect
Write
clear this bit
no effect
275
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