Usage Notes On Standby Mode - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL
9.6

Usage Notes on Standby Mode

Note the following items when using the standby modes:
• Switching to a standby mode and Interrupt
• Release of the standby mode by an Interrupt
• Release of the Stop mode by an Interrupt
• Oscillation stabilization wait time after Stop mode release
• Clock mode switching
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Switching to a Standby Mode and Interrupt
When there is a pending interrupt request to the CPU, writing to the SMS bits in the SMCR register has no
effect. In other words, the desired mode transition is not performed even after the interrupt service is
completed. If the interrupt request is already cleared and if there are no other pending requests, the desired
mode transition can be performed. Note that this behavior is not dependent on whether the setting in the PS
register allows the CPU to accept the interrupt request.
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Release of the Standby Mode by an Interrupt
If an NMI or an interrupt request of interrupt priority level higher than seven is issued from a peripheral
function during Sleep, Timer or Stop mode, the standby mode is released, which does not depend on whether
the CPU accepts the interrupt.
After the release of the standby mode by an interrupt, normal processing is performed.
If the interrupt is accepted, the CPU first executes the remaining instructions in the pipeline as to the state
before entering the standby mode. Then it continues with normal interrupt processing.
If the interrupt is not accepted, the CPU continues with the execution of the instructions in the pipeline and
the following instructions.
In case the voltage regulator was manually set to Low Power mode during Sleep or Timer mode (by setting
the SMCR:LMPSS bit), the wakeup is delayed by typ. 40µs for the stabilization of the voltage regulator.
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Release of the Stop Mode by an Interrupt
The Stop mode can be released by an external interrupt or by an NMI. As an external interrupt input cause, a
H-level signal, L-level signal, rising edge, or falling edge can be selected.
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Oscillation stabilization wait time after Stop mode release
Because all oscillators are halted in the Stop mode, an oscillation stabilization wait time is required. The
setting of the SC1S and SC2S bits of the CKSR register define which clock is used after wakeup from Stop
mode by interrupt. Oscillators and the PLL clock are enabled depending on the RCE, MCE, PCE, SCE, SC1S
and SC2S bits and stabilization times are applied according to the setting of the clock stabilization select
register (CKSSR). The CPU starts operating after stabilization of the System clock 1, selected by the SC1S
bit. Modules using the System clock 2 start operating after stabilization of the System clock 2. The clocks
selected by the SC1S and SC2S bits are always enabled, independent of the setting of the clock enable bits
(RCE, MCE, PCE and SCE).
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