Fujitsu MB91150 Series Hardware Manual

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Page 3 FR30 32-BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 PREFACE I Objectives and Intended Reader The MB91150 Series, hereafter referred to as MB91150, is a member of the "32-bit single-chip microcontroller FR30 Series" family and has a CPU based on a new RISC architecture at its core. This single-chip microcontroller contains peripheral I/O resources suited for audio equipment and MD drives that require low power consumption.
Page 6 I Structure of This Manual This manual contains 21 chapters and one appendix. CHAPTER 1 "OVERVIEW OF THE MB91150" This chapter provides basic items that are required to fully understand the MB91150, such as a description of MB91150 features, block diagrams, and an outline of functions. CHAPTER 2 "HANDLING THE DEVICE"...
Page 7 CHAPTER 14 "8-BIT D/A CONVERTER" This chapter describes the 8-bit D/A converter. It also describes the operation of the converter, block diagram, and the structures and functions of the converter registers. CHAPTER 15 "UART" This chapter describes the UART and provides its block diagram. It also describes pins, structures and functions of registers, interrupts, timing, baud rates, and device operation.
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9 READING THIS MANUAL I Details Regarding the Manual Format An explanation of the most important terms in this manual is given in the table below. Term Meaning I-BUS 16-bit bus for internal instructions. The FR Series employs internal Harvard architecture; there are independent buses for instructions and data. A bus converter is connected to the I-BUS.
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW OF THE MB91150 ..............1 MB91150 Features ..........................2 Block Diagrams ............................5 Package Dimensions ..........................7 Pin Assignment ............................9 Pin Functions ............................12 I/O Circuit Types ..........................20 CHAPTER 2 HANDLING THE DEVICE ................23 Notes on Handling Devices .........................
Page 12 3.12.1 Stop Status ............................ 89 3.12.2 Sleep Status ..........................92 3.12.3 Status Transition of the Low-power Consumption Mode .............. 95 CHAPTER 4 BUS INTERFACE ..................97 Outline of Bus Interface ........................98 Block Diagram of the Bus Interface ....................100 Registers of the Bus Interface ......................
Page 13 Block Diagram of the 8/16-bit Up/Down Counter/Timer ..............166 List of Registers of the 8/16-Bit Up/Down Counter/Timer ..............168 6.3.1 Counter Control Register H/L (CCRH/L) ..................169 6.3.2 Counter Control Register H/L ch1 (CCR H/L Ch1) ............... 173 6.3.3 Counter status register 0/1 (CSR0/1) ................... 174 6.3.4 Up/down count register 0/1 (UDCR 0/1) ..................
Page 14 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK ......... 247 10.1 Overview of External Interrupt ......................248 10.2 External Interrupt Registers ......................249 10.2.1 Enable Interrupt Register (ENIRn) ....................250 10.2.2 External Interrupt Request Register (EIRRn) ................251 10.2.3 External Interrupt Level Setting Register (ELVR: External Level Register) ......... 252 10.3 External Interrupt Operation ......................
Page 15 15.2 UART Block Diagram ......................... 306 15.3 UART Pins ............................308 15.4 UART Registers ..........................311 15.4.1 Control register (SCR0-3) ......................312 15.4.2 Mode register (SMR0-3) ....................... 314 15.4.3 Status register (SSR0-3) ......................316 15.4.4 Input-data register (SIDR0-3), output-data register (SODR0-3) ........... 318 15.4.5 Communication prescaler control register (CDCR) ..............
Page 16 17.7.1 Timing charts for the descriptor access section ................385 17.7.2 Timing charts for the data transfer section ................... 387 17.7.3 Timing charts for transfer termination in continuous transfer mode ..........389 17.7.4 Timing charts for the transfer termination operation ..............391 CHAPTER 18 BIT-SEARCH MODULE ................
Page 17: Chapter 1 Overview Of The Mb91150
CHAPTER 1 OVERVIEW OF THE MB91150 This chapter provides basic information required to fully understand the MB91150, such as a description of MB91150 features, block diagrams, and an outline of functions. 1.1 "MB91150 Features" 1.2 "Comprehensive Block Diagram of MB91150" 1.3 "Exterior Dimensions"...
Page 18: Mb91150 Features
CHAPTER 1 OVERVIEW OF THE MB91150 MB91150 Features The MB91150 is a single-chip microcontroller with peripheral I/O resources suited for controlling devices such as audio equipment and MD drives that require operation with low-power consumption. The core of the MB91150 is a 32-bit RISC CPU (FR30 Series).
Page 19 CHAPTER 1 OVERVIEW OF THE MB91150 ❍ Internal RAM Mask product, FLASH product, EVA-FLASH product: 2 KB ❍ Internal data RAM • MB91FV150, MB91F155A, MB91155 • EVA-FLASH product, FLASH product, Mask product: 32 KB • MB91154 • Mask product: 20 KB ❍...
Page 20 CHAPTER 1 OVERVIEW OF THE MB91150 ❍ Serial I/O • UART x 4 channels. Each UART can perform clock-synchronized serial transfer with the LSB/MSB switching function. • Serial data output and serial clock output can be selected by open-drain or push-pull software.
Page 21: Block Diagrams
CHAPTER 1 OVERVIEW OF THE MB91150 Block Diagrams This section provides MB91150 block diagrams separately for individual packages. I Block diagram for MB91FV150, MB91F155A and MB91155 Figure 1.2-1 "Block diagram (MB91FV150, MB91F155A and MB91155)" is a block diagram for the MB91FV150, MB91F155A and MB91155. Figure 1.2-1 Block diagram (MB91FV150, MB91F155A and MB91155) FR30 CPU Core D-Bus...
Page 22 CHAPTER 1 OVERVIEW OF THE MB91150 I Block diagram for MB91154 Figure 1.2-2 "Block diagram (MB91154)" is a block diagram for the MB91154. Figure 1.2-2 Block diagram (MB91154) FR30 CPU Core D-Bus I-Bus Clock Calendar P37/D31(IO) PE7/OC7 Data RAM PE6/OC6 20KB PE5/OC5 P30/D24...
Page 23: Package Dimensions
2.54 ± 0.25 INDEX AREA (.155 ± .004) (.100 ± .010) 52.32 ± 0.56 1.27 ± 0.25 (.050 ± .010) (2.060 ± .022) + 0.41 + .016 5.59 (.220) MAX 3.40 (.134 Dimensions in mm (inches). 1994 FUJITSU LIMITED R299001SC-2-2...
Page 24 –0.10 (Mounting height) +.008 .059 –.004 0.10±0.10 (.004±.004) 0˚~8˚ INDEX (Stand off) 0.25(.010) 0.50±0.20 "A" (.020±.008) 0.60±0.15 LEAD No. (.024±.006) 0.50(.020) 0.22±0.05 0.08(.003) (.009±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003 FUJITSU LIMITED F144019S-c-4-6...
Page 25: Pin Assignment
CHAPTER 1 OVERVIEW OF THE MB91150 Pin Assignment This section shows the MB91150 pin assignment for each type of package. I Pin assignment of MB91FV150 (PGA-299C-A01) Figure 1.4-1 "MB91FV150 (PGA-299C-A01) pin assignment" shows the MB91FV150 (PGA- 299C-A01) pin assignment. Table 1.4-1 "Correspondence between pin numbers and pin names (MB91FV150 (PGA-299C-A01)) (Device: MB91FV150, Package: PGA-299C-A01)"...
Page 26 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.4-1 Correspondence between pin numbers and pin names (MB91FV150 (PGA-299C-A01)) (Device: MB91FV150, Package: PGA-299C-A01) Pin name Pin name Pin name Pin name Pin name Pin name P20/D16 P81/BGRNT PK1/AN1 PD4/INT12/ZIN0 OPEN OPEN P82/BRQ PK2/AN2 OPEN OPEN...
Page 27 CHAPTER 1 OVERVIEW OF THE MB91150 I Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) Figure 1.4-2 "Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01)" shows the MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) pin assignments. Figure 1.4-2 Pin assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) P20/D16...
Page 28: Pin Functions
CHAPTER 1 OVERVIEW OF THE MB91150 Pin Functions Table 1.5-1 "Functions of the MB91150 pins" lists the functions of the MB91150 pins. I Functions of the MB91150 pins Table 1.5-1 Functions of the MB91150 pins Pin No. Pin name Circuit type Function description P20/D16 External data bus bits 16 to 23...
Page 29 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description P60/A16 External address bus bits 16 to 23 P61/A17 Can be used as a port when the address bus is not P62/A18 used.
Page 30 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description High-speed clock oscillation pins (16.5 MHz) PC0/INT0 External interrupt request inputs 0 to 3 PC1/INT1 These inputs are always in use while the PC2/INT2 corresponding external interrupts are enabled.
Page 31 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description PD7/ATG/INT15 External interrupt request input 15 This input is always in use while the corresponding external interrupt is enabled. Stop port output in advance unless the resulting processing is intentional.
Page 32 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description PI4/SOT3 UART3 data output Effective when UART3 data output specification is enabled. Can be used as a port when UART3 data output specification is disabled.
Page 33 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description PH2/SCK0/TO0 UART0 clock I/O, Reload Timer 0 output Acts as output for Reload Timer 0 when UART0 clock output is disabled and Reload Timer 0 output is enabled.
Page 34 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description PL6/DREQ2 DMA external transfer request input This pin is always in use when the pin is selected for a DMA controller transfer source.
Page 35 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 pins (Continued) Pin No. Pin name Circuit type Function description 9,26, Ground level of digital circuit 44, 59, Be sure to ground the power supply to all V pins.
Page 36: I/O Circuit Types
CHAPTER 1 OVERVIEW OF THE MB91150 I/O Circuit Types Table 1.6-1 "I/O circuit types" shows the MB91150 I/O circuit types. I I/O circuit types Table 1.6-1 I/O circuit types Classification Circuit Remarks • High-speed oscillator (16.5 MHz) Oscillation feedback resistor: about 1 MΩ...
Page 37 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.6-1 I/O circuit types Classification Circuit Remarks • CMOS hysteresis I/O pin CMOS level output CMOS hysteresis input Pout (With standby control) IOL=4mA Nout Hysteresis input Standby control • CMOS level input pin CMOS level input (Without standby control) Digital input...
Page 38 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.6-1 I/O circuit types Classification Circuit Remarks • Analog/CMOS level I/O pin Pout CMOS level output CMOS level input (With standby control) Nout Analog input (Analog input is enabled when the bit corresponding AIC is 1.) CMOS input IOL=4mA Standby control...
Page 39: Chapter 2 Handling The Device
CHAPTER 2 HANDLING THE DEVICE This chapter provides details on handling the MB91150. 2.1 "Notes on Handling the MB91130" 2.2 "Notes on Using Devices" 2.3 "Power-On"...
Page 40: Notes On Handling Devices
CHAPTER 2 HANDLING THE DEVICE Notes on Handling Devices This section describes latch-up prevention, pin processing, and circuit handling. I Latch-up prevention CMOS ICs may suffer a latch-up when a higher voltage than V or a lower voltage than V applied to an input or output pin or when a voltage exceeding the applicable rating is applied between V and V...
Page 41 CHAPTER 2 HANDLING THE DEVICE I Circuit handling ❍ Crystal oscillation circuit Noise near the X0, X1, X0A, or X1A pin causes this device to malfunction. Design PC boards so that the X0 and X1 (X0A and X1A) pins, crystal oscillators (or ceramic oscillators), and bypass capacitors to the ground can be placed as close as possible.
Page 42: Notes On Using Devices
CHAPTER 2 HANDLING THE DEVICE Notes on Using Devices This section provides notes on using external reset input and external clocks. I External reset input To securely put the device into the reset state, at least five machine cycles of L level input to the RST pin are required.
Page 43: Power-On
CHAPTER 2 HANDLING THE DEVICE Power-On This section provides notes on power-on and notes applicable when the clock function is not used. I Notes on power-on ❍ Power-on At power-on, be sure to start the RST pin at the L level. After the power supply level becomes the V level, wait until the time for at least five cycles of the internal operating clock has elapsed, then set the RST pin to the H level.
Page 44 CHAPTER 2 HANDLING THE DEVICE I When the clock function (calendar macro) Is not used When the clock function is not used, arrange the clock oscillation pins as shown in Figure 2.3-1 "Arrangement of clock oscillation pins when the clock function is not used". Figure 2.3-1 Arrangement of clock oscillation pins when the clock function is not used OPEN MB91150...
Page 45: Chapter 3 Memory Space, Cpu And Control Unit
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT This chapter provides basic information regarding the architecture, specifications, instructions, and other topics, that is required to understand the CPU core functions of the FR series. 3.1 "Memory Space" 3.2 "CPU Architecture" 3.3 "Programming Model"...
Page 46: Memory Space
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Memory Space The logical address space of the FR series is four gigabytes (2 addresses). The CPU accesses this space linearly. I Direct addressing area The following area of the address space is used for I/O operations. This area is called the direct addressing area.
Page 47 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Memory map for MB91FV150, MB91F155A and MB91155 Figure 3.1-1 "Memory map for MB91FV150, MB91F155A and MB91155" shows the memory space allocation for the MB91FV150, MB91F155A and MB91155. Figure 3.1-1 Memory map for MB91FV150, MB91F155A and MB91155 External ROM Internal ROM external bus mode...
Page 48 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Memory map for MB91154 Figure 3.1-2 "MB91154 memory map" shows the memory space allocation for the MB91154. Figure 3.1-2 MB91154 memory map External ROM Internal ROM external bus mode external bus mode Single-chip mode 0000 0000 Direct addressing area...
Page 49: Cpu Architecture
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT CPU Architecture The FR CPU is a high-performance core employing RISC architecture and using high- level function instructions for insertion. I Features ❍ Use of the RISC architecture ❍ Basic instructions, one instruction for one cycle ❍...
Page 50 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Internal architecture The FR CPU uses the Harvard architecture in which the instruction bus and data bus are mutually independent. The bus converter for 32 bits <--> 16 bits is connected to the data bus (D-BUS) to provide the interface between the CPU and peripheral resources.
Page 51 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Figure 3.2-2 Instruction pipeline C L K Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instructions are not executed out of sequence. In other words, when instruction A enters the pipeline before instruction B, it will reach the write back stage before instruction B.
Page 52: Programming Model
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Programming Model This section describes the basic programming model and each register of the device. I Basic programming model Figure 3.3-1 "Basic programming mode" shows the basic programming model. Figure 3.3-1 Basic programming model 32 bits [Initial value] XXXX XXXX...
Page 53 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I General-purpose registers Figure 3.3-2 "General-purpose register configuration" shows the configuration of the general- purpose register. Figure 3.3-2 General-purpose register configuration 32 Bit [Initial value] XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000 Registers R0 to R15 are general-purpose registers.
Page 54 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Program status (PS) This register stores the program status. It is divided into three parts: ILM, SCR, and CCR. All the undefined bits in the figure are reserved. They always return 0 in read access. Writing operations have no effect.
Page 55 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT [Bit 3] Negative flag Indicates the sign when the arithmetic operation result is assumed to be an integer represented in twos-complement form. Value Content Indicates that the result of an arithmetic operation was a positive value. Indicates that the result of an arithmetic operation was a negative value.
Page 56 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT [Bits 10 and 9] Step division flag Stores intermediate data when executing step division. The flag must not be changed during the division operation. When another operation is performed while step division is being executed, the restart of the step division operation is assured by saving and restoring the value of the PS register.
Page 57 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Program counter (PC) [Initial value] XXXXXXX This register indicates the address of the instruction being executed. Bit 0 is set to 0 when updating the PC during instruction execution. Bit 0 may be set to 1 only when an odd address is specified as a branch destination address. However, bit 0 is invalid in this case, and the instruction must be placed at an address that is a multiple of 2.
Page 58 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I System stack pointer (SSP) [Initial value] 00000000 The SSP is a system stack pointer. When the S flag is 0, this register functions as R15. The SSP can be explicitly specified. At EIT generation, this register is also used for the stack pointer specifying the stack for saving the values of the PS and PC.
Page 59 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ❍ For division At the start of the operation, the dividend is stored in the MDL. When a division is performed by executing the DIV0S, DIV0U, DIV1, DIV2, DIV3, and DIV4 instructions, the result is stored in the MDL and MDH. •...
Page 60: Data Structure
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Data Structure The following data structures are used in the FR series: • Bit ordering: Little endian • Byte ordering: Big endian I Bit ordering FR uses little-endian bit ordering. Figure 3.4-1 "Bit configuration of data items according to bit ordering" shows the bit configuration of data items according to the specified bit ordering.
Page 61: Word Alignment
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Word Alignment Instructions and data are accessed in units of bytes. The address structure depends on the instruction length and data length. I Program access An FR program must be located at an address that is a multiple of 2. Bit 0 of the PC is set to 0 when the PC is updated during instruction execution.
Page 62: Special Memory Areas
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Special Memory Areas This section shows a memory map of the MB91150. I Special memory areas The address space for special memory areas is a 32-bit linear space. Figure 3.6-1 "MB91150 memory map" shows a memory map of the MB91150. Figure 3.6-1 MB91150 memory map 0000 0000 Byte data...
Page 63: Overview Of Instructions
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Overview of Instructions In addition to the general RISC instruction system, the FR series supports logical operation instructions and bit operation instructions that were optimized for insertion, and direct addressing instructions. Each instruction is at least 16 bits long (some instructions are 32 or 48 bits long), which makes for excellent memory use efficiency.
Page 64 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ❍ Logical operation and bit operation The logical operation instructions can perform the logical operations AND, OR, and EOR between general-purpose registers and between a general-purpose register and memory (and I/ O). The bit operation instructions can directly change the contents of the memory (and I/O). General register indirect memory addressing is supported.
Page 65: Operations With Delay Slots
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.7.1 Operations with Delay Slots During operations with delay slots, a branch occurs at an instruction immediately after a branch instruction (called a delay slot) before the branch destination instruction is executed. I Branch instructions with delay slots The following branch instructions with delay slots are provided: JMP:D...
Page 66 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ❍ Ri to be referenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even if an instruction in a delayed slot updates Ri. [Example] LDI:32 #Label, R0 JMP:D ; Branch to Label LDI:8 #0, R0 ;...
Page 67 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Restrictions on branch instructions with delay slots ❍ Instructions that can be placed in delay slots Only instructions that satisfy the following conditions can be executed in delay slots: • One-cycle instructions •...
Page 68: Branch Instructions Without A Delay Slot
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.7.2 Branch Instructions without a Delay Slot During operation without a delay slot, the instructions are executed in the order of the instruction list. I Branch instructions without a delay slot The following branch instructions without a delay slot are supported: CALL label12 CALL...
Page 69: Eit (Exception, Interrupt, And Trap)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT EIT (Exception, Interrupt, and Trap) EIT indicates that a program being executed is suspended by an event for the purpose of executing another program. EIT is the generic name for exception, interrupt, and trap.
Page 70: Interrupt Level
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.8.1 Interrupt Level The interrupt levels are 0 to 31 and are controlled with five bits. I Interrupt level Table 3.8-1 "Interrupt level" shows the assignment of each interrupt level. Table 3.8-1 Interrupt level Interrupt level Binary Decimal...
Page 71: Interrupt Stack Operation
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.8.2 Interrupt Stack Operation This area is indicated by the system stack pointer (SSP). PC and PS values are saved in, or restored from this area. After an interrupt, the PC is stored at the address indicated by the SSP and the PS is stored at the address of (SSP + 4).
Page 72: Eit Vector Table
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.8.3 EIT Vector Table The table base register (TBR) indicates the first address of the EIT vector table. The vector area for EIT is a 1-KB area starting at the address indicated by the table base register (TBR).
Page 73 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Table 3.8-2 Vector table Vector No. Vector address Explanation 000FFFFC Reset TBR + 03F8 System-reserved TBR + 03F4 System-reserved TBR + 03F0 System-reserved TBR + 03EC System-reserved TBR + 03E8 System-reserved TBR + 03E4 System-reserved TBR + 03E0 Coprocessor absence trap...
Page 74: Multiple Eit Processing
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.8.4 Multiple EIT Processing If two or more EIT sources occur at the same time, the CPU selects and accepts one EIT source. After executing the EIT sequence, the CPU repeats monitoring for EIT sources.
Page 75 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Table 3.8-4 EIT handler execution order Handler execution order Source Reset Undefined instruction exception Step trace trap INTE instruction (NMI) INT instruction User interrupt Coprocessor absence trap Coprocessor error trap *1: The other sources are discarded. *2: If the INTE instruction is subject to step execution, only the EIT for the step trace trap occurs.
Page 76: Eit Operation
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.8.5 EIT Operation This section describes EIT operation. Assume that the PC of the transfer source in the explanation below indicates the address of the instruction for which an EIT source was detected. "Address of the next instruction"...
Page 77 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 6. 0 --> S flag 7. (TBR + vector offset of the accepted interrupt request) --> PC At the end of the interrupt sequence, the CPU detects a new EIT before executing the first instruction of the handler.
Page 78 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Operation for step trace trap If the T flag in SCR of the PS is set and the step trace function is enabled, a trap occurs and a break in processing occurs each time one instruction is executed. ❍...
Page 79 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT The address of the instruction that detected the undefined instruction exception is saved in the I Coprocessor absence trap If there is an attempt to execute a coprocessor instruction for a coprocessor that is not mounted, a coprocessor absence trap occurs.
Page 80: Reset Sequence
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Reset Sequence This section describes the reset operation for placing the CPU in operation status. I Reset sources The causes for reset are as follows: • Input from an external reset pin •...
Page 81: Operation Mode
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.10 Operation Mode The FR Series controls the operation mode using the mode pins (MD2, 1, 0) and mode register (MODR). I Operation mode Two operation modes, bus mode and access mode, are used. Bus mode Access mode Single chip...
Page 82 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Mode data The data written at "0000 07FF " by the CPU after a reset is called mode data. A mode register (MODR) is allocated at "0000 07FF ". After data is set in this register, the system runs in the mode specified by this register.
Page 83: Clock Generator (Low-Power Consumption Mechanism)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11 Clock Generator (Low-Power Consumption Mechanism) The clock generator is a module for the following functions: • CPU clock generation (this includes the gear function) • Peripheral clock generation (this includes the gear function) •...
Page 84 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Block diagram of the clock generator Figure 3.11-2 "Block diagram of the clock generator" shows the block diagram of the clock generator. Figure 3.11-2 Block diagram of the clock generator [Gear control block] GCR register CPU gear Peripheral...
Page 85: Reset Source Register (Rsrr) And Watchdog Cycle Control Register (Wtcr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) The reset source register (RSRR) is used to store the type of the generated reset. The watchdog cycle control register (WTCR) is used to specify the cycle of the watchdog timer.
Page 86 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Interval of writing to the Time from writing the last required minimum WPR to 5AH to the WPR to suppress watchdog reset watchdog reset generation generation φ x 2 φ x 2 to φ...
Page 87: Standby Control Register (Stcr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.2 Standby Control Register (STCR) The standby control register (STCR) controls standby operation and specifies the oscillation stabilization wait time. I Standby control register (STCR) The register is configured as follows: Initial value STCR STOP SLEP...
Page 88: Time-Base Timer Clear Register (Ctbr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.3 Time-base Timer Clear Register (CTBR) This register is used to initialize the time-base timer to 0. I Time-base timer clear register (CTBR) The register is configured as follows: Initial value CTBR XXXX XXXX 000483 ( W )
Page 89: Gear Control Register (Gcr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.4 Gear Control Register (GCR) This register controls the gear function of the CPU and peripheral system clocks. I Gear control register (GCR) The register is configured as follows: Initial value CCK1 CCK0 DBLAK DBLON PCK1 PCK0...
Page 90 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ❍ [Bit 4] DBLON This bit specifies the operation status of the clock doubler. It is initialized at reset. DBLON Internal operating frequency: same as external operating frequency Operating in 1:1 relationship [Initial value] Operating in 2:1 relationship [Bits 3 and 2]: PCK1 and PCK0 These bits specify the peripheral system gear cycle.
Page 91: Watchdog Reset Generation Delay Register (Wpr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.5 Watchdog Reset Generation Delay Register (WPR) The watchdog reset generation delay register is used for clearing the watchdog timer flip-flop. It can delay the watchdog reset generation. I Watchdog reset generation delay register (WPR) The register is configured as follows: Initial value XXXX XXXX...
Page 92: Dma Request Suppression Register (Pdrr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.6 DMA Request Suppression Register (PDRR) The DMA request suppression register temporarily suppresses a DMA request so as to enable CPU operation. I DMA request suppression register (PDRR) The register is configured as follows: Initial value PDRR ——0000...
Page 93: Pll Control Register (Pctr)
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.7 PLL Control Register (PCTR) The PLL control register controls PLL oscillations. The setting of this register can be changed only when GCR CHC is 1. I PLL control register (PCTR) The PLL control register (PCTR) has the following configuration: Initial value PCTR SLCT1...
Page 94: Watchdog Function
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.8 Watchdog Function The watchdog function can detect a "program crashed" status. Assume that A5 could not be written to the watchdog reset delay register within the given time due to a program crash. In this case, the watchdog timer generates a watchdog reset request.
Page 95 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Delaying reset generation Once the watchdog timer is activated, the program must periodically write A5 and 5A to the watchdog reset delay register (WPR). The watchdog reset flip-flop stores the falling edge of the tap selected by the time-base timer. If this flip-flop is not cleared at the second falling edge, a reset is generated.
Page 96: Gear Function
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.9 Gear Function The gear function allows the elimination of some clock pulses from clock signals. It has two independent circuits: A CPU and a peripheral circuit. These circuits allow the exchange of data between the CPU and peripherals even when the gear ratio is different.
Page 97 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Settings of the gear function For the CPU clock control, the desired gear ratio can be set by setting the CCK1 and CCK0 bits of the gear control register (GCR) to the desired values. For the peripheral clock control, the desired gear ratio can be set by setting the PCK1 and PCK0 bits of that register to the desired values.
Page 98: Retaining A Reset Source
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.10 Retaining a Reset Source The system stores the last generated reset source. All related flags are set to 0 during a read access. A source flag that was set remains as long as it is not read. I Block diagram of the reset source retention circuit Figure 3.11-8 "Block diagram of the reset source retention circuit"...
Page 99 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Notes: • If the PONR bit is 1, consider the other bits as being undefined. When a check of reset sources is to be performed afterwards, be sure to place the instruction for confirming power- on reset at the beginning.
Page 100: Example Of Setting The Pll Clock
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.11.11 Example of Setting the PLL Clock This section gives an example of setting the PLL clock and also provides an example of the related assembler source code. I Example of setting the PLL clock Figure 3.11-9 "Example of setting the PLL clock"...
Page 101 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Reference chart for the clock system Figure 3.11-10 Reference chart for the clock system Divided-by-2 CCK1,0 DBLON system input 16.5MHz CPU system PLL system input Oscillation input Bus system SLCT0 CPU system gear 33MHz Peripheral system gear VSTP...
Page 102 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT Example of the related assembler source code (Example of switching to the PLL system) ; ******************************************* PLL Sample Program ; ******************************************* ; Load Setting Data ldi:20 #GCR, R0 ldi:20 #PCTR,R1 ldi:8 #GCR_MASK,R2 ;...
Page 103: Low-Power Consumption Mode
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.12 Low-Power Consumption Mode The low-power consumption mode has stop and sleep statuses. I Overview of the stop status The stop status means a state in which all internal clocks and oscillation circuit operation (except 32 kHz oscillation) are stopped.
Page 104 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Low-power consumption mode operations Table 3.12-1 "Low-power consumption mode operations" lists the low-power consumption mode operations. Table 3.12-1 Low-power consumption mode operations Internal clock Oscillator Operation Transition Peripheral Release method status condition CPU and Standard...
Page 105: Stop Status
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.12.1 Stop Status Stop status means the stoppage of all internal clocks and stoppage of the oscillation circuit. This status allows the minimizing of power consumption. I Block diagram of the stop control block Figure 3.12-1 "Block diagram of the stop control block"...
Page 106 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Transition to stop status ❍ Method of setting the stop status by using an instruction To enter stop status, set bit 7 of STCR to 1. After a stop request is issued, the CPU enters a status in which it is not using the internal bus. The clocks then stop in the following order: CPU clock -->...
Page 107 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT I Return from the stop status A return from the stop status can be achieved by an interrupt or by reset generation. ❍ Return with an interrupt When the interrupt enable bit for the peripheral function is valid, a return from the stop status is performed by generating a peripheral interrupt.
Page 108: Sleep Status
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.12.2 Sleep Status Sleep status means the stoppage of the CPU clock and internal bus clock. This status can reduce power consumption to some extent when no CPU operation is necessary. I Block diagram of the sleep control block Figure 3.12-2 "Block diagram of the sleep control block"...
Page 109 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT [Setting method] LDI:8 #11001100b,R1 ; CPU=Peripheral gear ratio(The following is an example of oscillation x 1/8), The value of CHC is arbitrary. LDI:32 #GCR,R2 R1,@R2 LDI:8 #01010000b,R1 ; SLEP=1 LDI:32 #STCR,R2 R1,@R2 I Return from the sleep status The return from the sleep status can be performed with an interrupt and by reset generation.
Page 110 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT ❍ Return by a reset request The system status changes from sleep status to ordinary operation status in the following order: 1. Internal reset generation 2. restart of supplying the internal bus clock signal 3.
Page 111: Status Transition Of The Low-Power Consumption Mode
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT 3.12.3 Status Transition of the Low-power Consumption Mode Figure 3.12-3 "Status transition of the low-power consumption mode" shows the status transition of the low-power consumption mode. I Status transition of the low-power consumption mode Figure 3.12-3 Status transition of the low-power consumption mode Power ON Reset status...
Page 112 CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT...
Page 113: Chapter 4 Bus Interface
CHAPTER 4 BUS INTERFACE This chapter provides an outline of the bus interface and describes bus operation. 4.1 "Outline of Bus Interface" 4.2 "Block Diagram of the Bus Interface" 4.3 "Registers of the Bus Interface" 4.4 "Bus Operation" 4.5 "Bus Timing" 4.6 "Internal Clock Multiply Operation (Clock Doubler)"...
Page 114: Outline Of Bus Interface
CHAPTER 4 BUS INTERFACE Outline of Bus Interface The bus interface controls the interface with external memory and external I/O units. I Bus interface features • 24-bit (16MB) address output • A bus width of 16 or 8-bit can be specified •...
Page 115 CHAPTER 4 BUS INTERFACE Figure 4.1-1 Examples of Allocating Chip Select Areas 00000000 00000000 CS1 (512K) 00080000 CS0 (512K) 00080000 CS0 (1M byte) 000FFFFF CS2 (1M byte) 000FFFFF 001FFFFF CS1 (64k byte) 0010FFFF CS3 (1M byte) CS2 (64k byte) 0011FFFF 002FFFFF CS3 (64k byte) 0012FFFF...
Page 116: Block Diagram Of The Bus Interface
CHAPTER 4 BUS INTERFACE Block Diagram of the Bus Interface Figure 4.2-1 "Block diagram of the bus interface block" shows a block diagram of the bus interface. I Bus interface block diagram Figure 4.2-1 Block diagram of the bus interface block A-Out External DATA Bus...
Page 117: Registers Of The Bus Interface
CHAPTER 4 BUS INTERFACE Registers of the Bus Interface Figure 4.3-1 "Registers of the bus interface" shows the registers of the bus interface. I Registers of the bus interface Figure 4.3-1 Registers of the bus interface Address 000 60C ASR1 Area Select Register 1 000 60E AMR1...
Page 118: Area Select Registers (Asr) And Area Mask Registers (Amr)
CHAPTER 4 BUS INTERFACE 4.3.1 Area Select Registers (ASR) and Area Mask Registers (AMR) The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify the ranges at which chip select areas 1 to 5 are allocated in address space. I Area select registers (ASR) and Area mask registers (AMR) The configurations of the ASRs and AMRs are as follows.
Page 119 CHAPTER 4 BUS INTERFACE 00000000 00000011 00000000 00000000 (00030000 00000000 00000011 11111111 11111111 (0003FFFF Example 2 ASR2 = 00001111 11111111 AMR2 = 00000000 00000011 In this example, "care" is set for the ASR2 bit when the corresponding AMR2 bit is 0, and a value of "1"...
Page 120: Area Mode Register 0 (Amd0)
CHAPTER 4 BUS INTERFACE 4.3.2 Area Mode Register 0 (AMD0) This register specifies the operating mode of chip select area 0 (space excluding the areas specified by ASR1 to ASR5 and AMR1 to AMR5). Area 0 is selected when the system is reset.
Page 121 CHAPTER 4 BUS INTERFACE [Bits 2 to 0]: WaiT Cycle bits (WTC2 to WTC0) WTC2 to WTC0 specify the number of wait cycles to be automatically inserted during normal bus interfacing. WTC2 WTC1 WTC0 Number of wait cycles to be inserted Note: WTC2 to WTC0 of AMD0 are set to 111 when the system is reset.
Page 122: Area Mode Register 1 (Amd1)
CHAPTER 4 BUS INTERFACE 4.3.3 Area Mode Register 1 (AMD1) This register specifies the operating mode of the chip select area 1 (specified by ASR1 and AMR1). I Area mode register 1 (AMD1) The configuration of Area mode register 1 (AMD1) is as follows: Initial value Access AMD1...
Page 123: Area Mode Register 32 (Amd32)
CHAPTER 4 BUS INTERFACE 4.3.4 Area Mode Register 32 (AMD32) This register specifies the operating mode of chip select area 2 (specified by ASR2 and AMR2) and chip select area 3 (specified by ASR3 and AMR3). BW1 and BW0 control the common bus width for areas 2 and 3. The number of wait cycles to be inserted can be set separately for areas 2 and 3.
Page 124: Area Mode Register 4 (Amd4)
CHAPTER 4 BUS INTERFACE 4.3.5 Area Mode Register 4 (AMD4) This register specifies the operating mode of chip select area 4 (specified by ASR4 and AMR4). I Area mode register 4 (AMD4) The configuration of Area mode register 4 (AMD4) is as follows: Initial value Access AMD4...
Page 125: Area Mode Register 5 (Amd5)
CHAPTER 4 BUS INTERFACE 4.3.6 Area Mode Register 5 (AMD5) This register specifies the operating mode of chip select area 5 (specified by ASR5 and AMR5). I Area mode register 5 (AMD5) The configuration of Area mode register 5 (AMD5) is as follows: Initial value Access AMD5...
Page 126: External Pin Control Register 0 (Epcr0)
CHAPTER 4 BUS INTERFACE 4.3.7 External Pin Control Register 0 (EPCR0) This register controls output of each signal. If output is allowed, a signal is output with the required timing in each bus mode. If input is enabled, inputs signal from an external circuit are accepted. If output is inhibited and input is disabled, the corresponding pin can be used as an I/O port.
Page 127 CHAPTER 4 BUS INTERFACE (The pins function as I/O ports.) (Initial value) • 1: BRQ input enabled, BGRNT output allowed [Bit 6]: ClocK output Enable bit (CKE) This bit enables output of the CLK (external bus operating clock pulse) • 0: Output inhibited •...
Page 128: External Pin Control Register 1 (Epcr1)
CHAPTER 4 BUS INTERFACE 4.3.8 External Pin Control Register 1 (EPCR1) This register controls output of address signals. I External pin control register 1 (EPCR1) The configuration of External pin control register 1 (EPCR1) is as follows: Initial value Access EPCR1 - -- ----- Initial value...
Page 129: Little-Endian Register (Ler)
CHAPTER 4 BUS INTERFACE 4.3.9 Little-endian Register (LER) The MB91150 ordinarily accesses the bus while treating all areas as big- endian areas. However, making the required settings in this register enables one of the areas 1 to 5 to be treated as a little-endian area. Note that area 0 cannot be treated as a little-endian area.
Page 130: Bus Operation
CHAPTER 4 BUS INTERFACE Bus Operation This section describes the bus operation based on the following topics: • Relationship between data bus width and control signals • Big-endian bus access • Little-endian bus access • Comparison of external access I Relationship between data bus width and control signals The relationship between the data bus width and control signals is described for the following bus interface: •...
Page 131: Relationship Between Data Bus Width And Control Signals
CHAPTER 4 BUS INTERFACE 4.4.1 Relationship Between Data Bus Width and Control Signals Control signals WR0 and WR1 always correspond to byte positions of the data bus in a one to one relationship regardless of whether the mode is big-endian or little-endian, and regardless of the data bus width.
Page 132: Bus Access In Big-Endian Mode
CHAPTER 4 BUS INTERFACE 4.4.2 Bus Access in Big-endian Mode Areas not specified in the LER are accessed through an external bus as a big-endian area. The FR series ordinarily uses big-endian access. I Data format The following figures show the relationship between internal registers and the external bus. ❍...
Page 133 CHAPTER 4 BUS INTERFACE ❍ Byte access (when an LDUB or STB instruction is executed) Figure 4.4-4 Relationship between internal register and external data bus for byte access (a) The lower byte of the (b) The lower byte of the output output address is 0.
Page 134 CHAPTER 4 BUS INTERFACE I External bus access Figure 4.4-7 "External bus access in big-endian mode (16-bit Bus)" and Figure 4.4-8 "External bus access in big-endian mode (8-bit Bus)" show external bus accesses under the following conditions: • Data bus width: 16 bits and 8 bits •...
Page 135 CHAPTER 4 BUS INTERFACE ❍ 16-bit bus Figure 4.4-7 External bus access in big-endian mode (16-bit bus) (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00"...
Page 136 CHAPTER 4 BUS INTERFACE ❍ 8-bit bus Figure 4.4-8 External bus access in big-endian mode (8-bit bus) (A) Word access (a)PA1/PA0='00' (b)PA1/PA0='01' (c)PA1/PA0='10' (d)PA1/PA0='11' (1) Output A1/A0 = '00' (1) Output A1/A0 = '00' (1) Output A1/A0 = '00' (1) Output A1/A0 = '00' (2) Output A1/A0 = '01' (2) Output A1/A0 = '01' (2) Output A1/A0 = '01'...
Page 137 CHAPTER 4 BUS INTERFACE I Example of connection with external devices Figure 4.4-9 "Example of a connection between the MB91150 and external devices" shows an example of connecting the MB91150 with external devices. Figure 4.4-9 Example of a connection between the MB91150 and external devices MB91150 *) For 16- and 8-bit devices, the data bus on the side of the MSB is used.
Page 138: Bus Access In Little-Endian Mode
CHAPTER 4 BUS INTERFACE 4.4.3 Bus Access in Little-endian Mode An area specified in the LER is accessed as a little-endian area through the external bus. The MB91150 accesses a little-endian area in the same bus access operation as for a big-endian area.
Page 139 CHAPTER 4 BUS INTERFACE I Data format Figure 4.4-10 "Relationship between internal register and external data bus (in word access)" to Figure 4.4-12 "Relationship between internal register and external data bus (byte access)" show the relationships between the internal register and external data bus for each data format. ❍...
Page 140 CHAPTER 4 BUS INTERFACE I Data bus width Figure 4.4-13 "Relationship between internal register and external data bus (16-bit bus)" to Figure 4.4-14 "Relationship between internal register and external bus for a 8-bit bus" show the relationships between the internal register and external data bus for each data bus width. ❍...
Page 141 CHAPTER 4 BUS INTERFACE I Examples of Connection with External Devices Figure 4.4-15 "Example of connecting the MB91150 with external devices (16-bit bus)" and Figure 4.4-16 "Example of connecting the MB91150 with external devices (8-bit bus)" show examples of connecting the MB91150 with external devices. ❍...
Page 142: Comparison Of External Access In Big-Endian And Little-Endian Mode
CHAPTER 4 BUS INTERFACE 4.4.4 Comparison of External Access in Big-endian and Little- endian Mode Table 4.4-1 "Comparison of external accesses between big-endian and little-endian modes (in word access)" to Table 4.4-3 "Comparison of external accesses between big-endian and little-endian modes (in byte access)" compare external accesses between big-endian and little-endian modes in terms of each data bus width and data format.
Page 143 CHAPTER 4 BUS INTERFACE I Half word access Table 4.4-2 Comparison of external accesses between big-endian and little-endian modes (in half word access) Big-endian mode Little-endian mode 16-bit bus Internal register External pins Control pins Internal register External pins Control pins address: "0"...
Page 144 CHAPTER 4 BUS INTERFACE Table 4.4-2 Comparison of external accesses between big-endian and little-endian modes (in half word access) (Continued) Big-endian mode Little-endian mode 8-bit bus Internal register External pins Control pins Internal register External pins Control pins address: "0" "1" address: "0"...
Page 145 CHAPTER 4 BUS INTERFACE I Byte access Table 4.4-3 Comparison of external accesses between big-endian and little-endian modes (in byte access) Big-endian mode Little-endian mode 16-bit bus Internal register External pins Control pins Internal register External pins Control pins address: "0" address: "0"...
Page 146 CHAPTER 4 BUS INTERFACE Table 4.4-3 Comparison of external accesses between big-endian and little-endian modes (in byte access) (Continued) Big-endian mode Little-endian mode 8-bit bus Internal register Internal register External pins Control pins External pins Control pins address: "0" address: "0" Internal register External pins Control pins Internal register...
Page 147: Bus Timing
CHAPTER 4 BUS INTERFACE Bus Timing This section provides detailed information on bus access operations in each of the following modes: • Normal bus access • Wait cycle • External bus request I Normal bus access With a normal bus interface, a basic bus cycle contains two clock cycles for both the read and write cycles.
Page 148: Basic Read Cycle
CHAPTER 4 BUS INTERFACE 4.5.1 Basic Read Cycle This section describes the operations of the basic read cycle. I Basic read cycle timing chart Figure 4.5-1 "Timing chart of the basic read cycle" shows an example of basic read cycle timing under the following conditions: •...
Page 149 CHAPTER 4 BUS INTERFACE according to the gear ratio. • A23 to A00 (address 23 to address 00) output the address of a leading byte location during word, half word or byte access in a read cycle starting with the start of a bus cycle (BA1). In the above example, a word is accessed in 16-bit access, and the address of the higher 16 bits of the word to be accessed (the lower two bits, indicating 0) is therefore output in the first bus cycle, while the address of the lower 16 bits is output in the second bus cycle (the lower...
Page 150: Basic Write Cycle
CHAPTER 4 BUS INTERFACE 4.5.2 Basic Write Cycle This section describes the operations of the basic write cycle. I Basic write cycle timing chart Figure 4.5-2 "Example of a timing chart of basic write cycle" shows an example of basic write cycle timing under the following conditions: •...
Page 151 CHAPTER 4 BUS INTERFACE BA1 falls and negated when BA2 falls D31 to D24 and D23 to D16 are asserted in accordance with WR0 and WR1 and the width of their data buses. In the above example, only WR0 is asserted because the data bus has a width of eight bits. •...
Page 152: Read Cycle In Each Mode
CHAPTER 4 BUS INTERFACE 4.5.3 Read Cycle in Each Mode Figure 4.5-3 "Sample read cycle timing chart 1" to Figure 4.5-7 "Sample read cycle timing chart 5" show examples of the read cycle timing in each mode. I Timing chart of read cycles in each mode ❍...
Page 153 CHAPTER 4 BUS INTERFACE ❍ Bus width: 8 bits Access: In units of half words Figure 4.5-6 Sample read cycle timing chart 4 A23-00 D31-24 D23-16 ❍ Bus width: 8 bits Access: In units of bytes Figure 4.5-7 Sample read cycle timing chart 5 A23-00 D31-24 D23-16...
Page 154: Write Cycle In Each Mode
CHAPTER 4 BUS INTERFACE 4.5.4 Write Cycle in Each Mode Figure 4.5-8 "Sample write cycle timing chart 1" to Figure 4.5-12 "Sample write cycle timing chart 5" show examples of the write cycle timing in each mode. I Write cycle timing in each mode ❍...
Page 155 CHAPTER 4 BUS INTERFACE ❍ Bus width: 8 bits Access: In units of half words Figure 4.5-11 Sample write cycle timing chart 4 A23-00 D31-24 D23-16 ❍ Bus width: 8 bits Access: In units of bytes Figure 4.5-12 Sample write cycle timing chart 5 A23-00 D31-24 D23-16...
Page 156: Mixed Read/Write Cycles
CHAPTER 4 BUS INTERFACE 4.5.5 Mixed Read/Write Cycles This section describes the operations of the read/write cycle. I Timing chart for mixed read/write cycles Figure 4.5-13 "Sample timing chart for mixed read/write cycles 1" shows examples of read/write cycle timing under the following conditions: •...
Page 157: Automatic Wait Cycle
CHAPTER 4 BUS INTERFACE 4.5.6 Automatic Wait Cycle This section describes the operations of the automatic wait cycle. I Automatic wait cycle timing chart Figure 4.5-14 "Sample timing chart for an automatic wait cycle" shows an example of automatic wait cycle timing under the following conditions: •...
Page 158: External Wait Cycle
CHAPTER 4 BUS INTERFACE 4.5.7 External Wait Cycle This section describes the operation of the external wait cycle. Timing chart of external wait cycle Figure 4.5-15 "Sample timing chart for an external wait cycle" shows an example of external wait cycle timing under the following conditions: •...
Page 159: External Bus Request
CHAPTER 4 BUS INTERFACE 4.5.8 External Bus Request This section describes the operations of external bus requests. I Releasing bus right Figure 4.5-16 Sample timing chart for releasing bus right high Z A23-00 #0:1 D31-16 #0:1 high Z high Z BGRNT One cycle [Operation]...
Page 160: Internal Clock Multiply Operation (Clock Doubler)
CHAPTER 4 BUS INTERFACE Internal Clock Multiply Operation (Clock Doubler) The MB91150 has a clock multiply circuit. The CPU internally operates at a frequency obtained by multiplying the bus interface frequency by one or two. The bus interface operates in synch with the CLK output pin regardless of the selected frequency. If an external access request is made from the CPU, external access starts after the CLK output goes high.
Page 161 CHAPTER 4 BUS INTERFACE Figure 4.6-2 Example of multiply-by-one clock timing Internal clock Internal instruction address N + 2 Internal instruction data D + 2 CLK output External address bus N + 2 N + 4 External data bus D + 2 External RD Pre-fetch External access (instruction fetch)
Page 162: Program Examples For The External Bus
CHAPTER 4 BUS INTERFACE Program Examples for the External Bus This section shows simple sample programs for operating the external bus. I Specification example of a program for external bus operation ❍ Registers are set as follows: • Areas • Area 0 (AMD0): 16 bits, normal bus, automatic wait - 0 •...
Page 163 CHAPTER 4 BUS INTERFACE I Program example for external bus operation The explanation of this example assumes that writing to a byte register is performed in units of bytes while writing to half word registers is performed in units of half words. ***** Program example *****...
Page 164 CHAPTER 4 BUS INTERFACE init_ler ldi:8 #0x02,r0 // CS2 little-endian ldi:20 #0x7fe,r1 // ler register address setting r0,@r1 // ler register write init_modr ldi:8 #0x80,r0 // External ROM external bus ldi:20 #0x7ff,r1 // modr register address setting r0,@r1 // modr register write //External bus access adr_set ldi:32...
Page 165: Chapter 5 I/O Ports
CHAPTER 5 I/O PORTS This chapter describes the I/O ports and provides the block diagrams of individual ports. It also describes the register configurations. 5.1 "Overview of I/O Ports" 5.2 "Block Diagram of Basic I/O Port" 5.3 "Block Diagram of I/O Ports (Including the Pull-up Resistor)" 5.4 "Block Diagram of I/O ports (Including the Open-drain Output and the Pull- up Resistor)"...
Page 166: Overview Of I/O Ports
CHAPTER 5 I/O PORTS Overview of I/O Ports This section provides I/O port block diagrams for the device and an outline of registers. I I/O port block diagrams The MB91150 supports using a pin as an I/O port when the pin is not set to be used for input or output of the resource corresponding to the pin.
Page 167: Block Diagram Of Basic I/O Port
CHAPTER 5 I/O PORTS Block Diagram of Basic I/O Port This section provides a block diagram of a basic I/O port. I Block diagram of basic I/O port Figure 5.2-1 "Block diagram of I/O ports" shows the basic configuration of the I/O ports. Figure 5.2-1 Block diagram of I/O ports Data Bus Resource input...
Page 168: Block Diagram Of I/O Ports (Including The Pull-Up Resistor)
CHAPTER 5 I/O PORTS Block Diagram of I/O Ports (Including the Pull-up Resistor) This section provides a block diagram of an I/O port with a pull-up resistor. I Block diagram of I/O port with a pull-up resistor Figure 5.3-1 "Block diagram of a port including the pull-up resistor" shows a block diagram of an I/O port with a pull-up resistor.
Page 169: Block Diagram Of I/O Ports (Including The Open-Drain Output And The Pull-Up Resistor)
CHAPTER 5 I/O PORTS Block Diagram of I/O ports (Including the Open-drain Output and the Pull-up Resistor) This section provides a block diagram of an I/O port with open-drain output function and a pull-up resistor. I Block diagram of I/O port with open-drain output function and pull-up resistor Figure 5.4-1 "Block diagram of a port including the open-drain output and the pull-up resistor"...
Page 170 CHAPTER 5 I/O PORTS Notes: • Pull-up resistor control register (PCR): Specifies whether to turn the pull-up resistor on or off. 0: Pull-up resistor is OFF 1: Pull-up resistor is ON • Open-drain control register (ODCR): Specifies whether the port is used for standard output or open-drain output.
Page 171: Block Diagram Of I/O Port (With Open-Drain Output Function)
CHAPTER 5 I/O PORTS Block Diagram of I/O Port (With Open-Drain Output Function) This section provides a block diagram of an I/O port with open-drain output function. I Block diagram of I/O port with open-drain output function Figure 5.5-1 "Block diagram of I/O port with open-drain output function" shows a block diagram of an I/O port with open-drain output function.
Page 172: Port Data Register (Pdr)
CHAPTER 5 I/O PORTS Port Data Register (PDR) The port data registers (PDR2 to PDR1) are I/O data registers of the I/O ports. The corresponding data direction registers (DDR2 to DDR1) control input and output. I Port data register (PDR) The register configuration of the port data register (PDR) is shown below.
Page 173: Data Direction Register (Ddr)
CHAPTER 5 I/O PORTS Data Direction Register (DDR) The data direction registers (DDR2 to DDR1) control in units of bits whether the corresponding I/O ports perform input or output. When 0 is set, input is performed, when 1 is set, output is performed. I Data direction register (DDR) The register configuration of the data direction register (DDR) is shown below.
Page 174 CHAPTER 5 I/O PORTS Note: DDRI bit 6 is a test bit. Always set the bit to 0. The value read from this bit is always 0.
Page 175: Pull-Up Control Register (Pcr)
CHAPTER 5 I/O PORTS Pull-up Control Register (PCR) Each of the pull-up resistor control registers (PCR1 to PCR6) specifies controls the pull-up resistor for the corresponding I/O port in input mode. • PCR = 0: Disables the pull-up resistor in input mode. •...
Page 176: Open-Drain Control Register (Odcr)
CHAPTER 5 I/O PORTS Open-Drain Control Register (ODCR) Each of the open-drain control registers (OCRH and OCRI) specifies whether the corresponding I/O port is used for standard output or open-drain output while the port is used in output mode. • OCR = 0: Standard output port •...
Page 177: Analog Input Control Register (Aicr)
CHAPTER 5 I/O PORTS 5.10 Analog Input Control Register (AICR) The analog input control register (AICR) controls the pins of the corresponding I/O port as follows: • AIC = 0: Port input mode • AIC = 1: Analog input mode The AIC is cleared to 0 by resetting.
Page 178 CHAPTER 5 I/O PORTS...
Page 179: Chapter 6 8/16-Bit Up/Down Counter/Timer
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER This chapter describes the 8/16-bit up/down counter/timer, their configurations and functions of the registers, as well as the operation of the 8/16-bit up/down counter/ timer. 6.1 "Overview of 8/16-Bit Up/Down Counter/Timer" 6.2 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer" 6.3 "List of Registers of the 8/16-Bit Up/Down Counter/Timer"...
Page 180: Overview Of 8/16-Bit Up/Down Counter/Timer
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Overview of 8/16-Bit Up/Down Counter/Timer The 8/16-bit up/down counter/timer consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits. I Characteristics of the 8/16-bit up/down counter/timer • With the 8-bit count register, counting can be performed in a range between 0 and 255 (decimal numbers).
Page 181 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER • With the count direction flag, the counting direction immediately before the current count can be identified. • The generation of interrupts when a compare match occurs, at reload (underflow), at overflow, or when the counting direction changes, can be controlled individually.
Page 182: Block Diagram Of The 8/16-Bit Up/Down Counter/Timer
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Block Diagram of the 8/16-bit Up/Down Counter/Timer This section provides block diagrams of the 8/16-bit up/down counter/timer. I Block diagram of the 8/16-bit up/down counter/timer ❍ Channel 0 Figure 6.2-1 "Block diagram of the 8/16-bit up/down counter/timer (channel 0)" shows a block diagram of the 8/16-bit up/down counter/timer (for Channel 0).
Page 183 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ❍ Channel 1 Figure 6.2-2 "Block diagram of the 8/16-bit up/down counter/timer (channel 1)" shows a block diagram of the 8/16-bit up/down counter/timer (for Channel 1). Figure 6.2-2 Block diagram of the 8/16-bit up/down counter/timer (channel 1) Data bus 8bit RCR1 (Reload/compare register 1)
Page 184: List Of Registers Of The 8/16-Bit Up/Down Counter/Timer
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER List of Registers of the 8/16-Bit Up/Down Counter/Timer This section provides a listing of 8/16-bit up/down counter/timer registers. I List of Registers of the 8/16-bit up/down counter/timer Figure 6.3-1 "List of registers of the 8/16-bit up/down counter/timer" lists the registers of the 8/ 16-bit up/down counter/timer.
Page 185: Counter Control Register H/L (Ccrh/L)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.1 Counter Control Register H/L (CCRH/L) This section describes the counter control register high/low (ch0). I Counter control register high/low ch0 (CCR H/L ch0) The structure of the counter control register high/low (ch 0) is shown below: Initial value Address: 000060 M16E CDCF CFIE...
Page 186 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 14] CDCF: Count direction change flag This flag is set when the count direction is changed. When the count direction is changed from up to down or down to up during counting, this flag is set to 1. 0: Writing 0 clears the setting.
Page 187 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [Bits 9 and 8] CES1 and CES0: Count clock edge selection bit In up/down counting mode, this bit selects the detection edge of external pins AIN and BIN. This setting is invalid in modes other than up or down counting mode. CES1 CES0 Selection edge...
Page 188 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 2] CGSC: Counter clear/gate selection bit This bit selects the function of the external pin ZIN. CGSC ZIN function Counter clear function (initial value) Gate function [Bits 1 and 0] CGE1 and CGE0: Counter clear/gate edge selection bit This bit selects the detection edge/level of the external pin ZIN.
Page 189: Counter Control Register H/L Ch1 (Ccr H/L Ch1)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.2 Counter Control Register H/L ch1 (CCR H/L Ch1) This section describes the counter control register high/low (ch1). I Counter control register high/low ch1 (CCR H/L ch1) The structure of the counter control register high/low (ch1) is shown below: Initial value Address: 000064 CDCF CFIE...
Page 190: Counter Status Register 0/1 (Csr0/1)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.3 Counter status register 0/1 (CSR0/1) The register configuration of counter status register 0/1 (CSR0/1) is shown below. I Counter status register 0/1 (CSR0/1) The structure of counter status register 0/1 is shown below: b i t Initial value Address: 000063 00000000...
Page 191 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] CMPF: Compare detection flag This flag indicates that the comparison result of the UDCR value and RCR value is that the values are equal. In write operations, the flag can only be set to 0, not to 1. CMPF Meaning of flag Comparison result does not match (initial value).
Page 192: Up/Down Count Register 0/1 (Udcr 0/1)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.4 Up/down count register 0/1 (UDCR 0/1) The register configuration of the up/down count register 0/1 (UDCR 0/1) is shown below. I Up/down count register 0/1 (UDCR 0/1) The structure of the up/down count register 0/1 is shown below: Initial value Address: 00005E 00000000...
Page 193: Reload/Compare Register 0/1 (Rcr 0/1)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.5 Reload/compare Register 0/1 (RCR 0/1) The register configuration of the reload/compare register 0/1 (RCR 0/1) is shown below. I Reload/compare register 0/1 (RCR 0/1) The structure of the reload/compare register 0/1 is shown below: Initial value 00000000 Address: 00005C...
Page 194: Selection Of Counting Mode
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Selection of Counting Mode This timer/counter has four counting modes. The CMS1 and CMS0 bits of the CCR register can be used to select these counting modes. I Selecting counting mode Table 6.4-1 "Selecting timer counting mode" lists the count modes that can be selected by the CMS1 and CMS0 bits.
Page 195 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER multiplication mode, count up if the AIN is faster, and count down if the BIN is faster. ❍ Multiply-by-2 mode In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period between the rising and falling edges of the BIN pin.
Page 196 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER rotations can be obtained and the rotation direction can be detected as well. When this counting mode is selected, the selection of the detection edge with USS1, USS0, DSS1 and DSS0 is invalid.
Page 197: Reload And Compare Functions
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Reload and Compare Functions The 8/16-bit up/down counter/timer have the reload and compare functions. These two functions can be combined for processing. I Example for selection of reload and compare function Table 6.5-1 "Selecting the detection edge" shows an example for the selection of the reload/ compare function.
Page 198 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER I When the compare function is enabled The compare function can be used in all modes other than timer mode. When the compare function is started, if the value of RCR and the value of UDCR match, CMPF is set and an interrupt request is generated.
Page 199 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Figure 6.5-3 Overview of the operation when the reload and compare functions are started at the same time Compare match Compare match Reload Reload Reload Compare match Counter clear Counter clear Underflow Underflow Underflow Counter clear An interrupt to the CPU can be generated at a compare match or at reload (underflow).
Page 200 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER UDCR 065h 080h Reload/clear event Clear by compare is performed when the values of the UDCR and the RCR match and while counting up. If down counting is performed or counting is stopped, the clear operation is not performed even when the values of the UDCR and the RCR match.
Page 201: Writing Data To The Up/Down Count Register (Udcr)
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Writing data to the up/down count register (UDCR) Data cannot be written to the up/down count register (UDCR) directly from the data bus. This section describes the procedure for writing, counter clearing, and flags of the device.
Page 202 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER I Count direction flag The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting operation preceding the current operation was counting up or down. Based on the counter clock signal from the input of the AIN and BIN pins, this value of this flag changes for each count.
Page 203: Chapter 7 16-Bit Reload Timer
CHAPTER 7 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of the timer registers, and the operations of the 16-bit reload timer. The chapter also provides a block diagram of the 16-bit reload timer. 7.1 "Overview of 16-bit Reload Timer"...
Page 204: Overview Of 16-Bit Reload Timer
CHAPTER 7 16-BIT RELOAD TIMER Overview of 16-bit Reload Timer The 16-bit reload timer consists of the following elements: • 16-bit down counter • 16-bit reload register • Internal count clock generation prescaler • Control register I Features of 16-bit reload timer •...
Page 205: Block Diagram Of A 16-Bit Reload Timer
CHAPTER 7 16-BIT RELOAD TIMER Block diagram of a 16-bit reload timer Figure 7.2-1 "Block diagram of the 16-bit reload timer" shows a block diagram of the 16-bit reload timer. I Block diagram of the 16-bit reload timer Figure 7.2-1 Block diagram of the 16-bit reload timer 16-bit reload register Reload RELD...
Page 206: Registers Of 16-Bit Reload Timer
CHAPTER 7 16-BIT RELOAD TIMER Registers of 16-bit Reload Timer Figure 7.3-1 "Register list of 16-bit reload timer" lists the registers of the 16-bit reload timer. I Register list of the 16-bit reload timer Figure 7.3-1 Register list of 16-bit reload timer CSL1 CSL0 MOD2 MOD1 (TMCSR)
Page 207: Control Status Register (Tmcsr)
CHAPTER 7 16-BIT RELOAD TIMER 7.3.1 Control status register (TMCSR) This register controls the operation mode and interrupts of the 16-bit timer. Bits other than UF, CNTE, and TRG can be rewritten only when CNTE = 0. Concurrent writing can be performed. I Control status register (TMCSR) The register configuration of the control status register (TMCSR) is shown below.
Page 208 CHAPTER 7 16-BIT RELOAD TIMER [Bit 4] RELD: This is a reload enable bit.When this bit is set to 1,the reload mode is entered, and if the counter value underflows from 0000 to FFFF , the counter loads the reload register value and continues operating.
Page 209: 16-Bit Timer Register (Tmr) And 16-Bit Reload Register (Tmrlr)
CHAPTER 7 16-BIT RELOAD TIMER 7.3.2 16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) The 16-bit timer register (TMR) reads the count value from the 16-bit timer. The initial value of this register is undefined. The 16-bit reload register (TMRLR) retains the initial count value. The initial value of this register is undefined.
Page 210: Internal Clock Operation
CHAPTER 7 16-BIT RELOAD TIMER Internal Clock Operation When the timer is driven by a divided-by internal clock, the clock source can be selected from 1/2, 1/8, and 1/32 of the machine clock. I Internal clock operation To start counting immediately after counting is enabled, set the CNTE and TRG bits of the control status register to 1.
Page 211: Underflow Operation
CHAPTER 7 16-BIT RELOAD TIMER Underflow operation A transition of a counter value from 0000 to FFFF is called "underflow". An underflow occurs when the [set value in the reload register + 1] count is reached. I Underflow operation When an underflow occurs, and the RELD bit in the control register is 1, the counter loads the value in the reload register and continues counting.
Page 212 CHAPTER 7 16-BIT RELOAD TIMER I Function of output pin The TO(0-3) output pin operates as toggled output reversed by underflowing at the reload mode, and as pulse output meaning the counting operation at the one-shot mode. The output polarity can be set by the OUTL bit of the register. When the OUTL bit is set to 0, the TO(0-3) output pin outputs initial value 0 as toggled output, and value 1 as the one-shot pulse output during counting operation.
Page 213: Counter Operation States
CHAPTER 7 16-BIT RELOAD TIMER Counter Operation States The state of the counter depends on the CNTE bit of the control register and the WAIT signal generated internally. The states that can be set are the stop state (STOP state) for CNTE = 0 and WAIT = 1, the start trigger waiting state (WAIT state) for CNTE = 1 and WAIT = 1, and the operational state (RUN state) for CNTE = 1 and WAIT = 0.
Page 214 CHAPTER 7 16-BIT RELOAD TIMER...
Page 215: Chapter 8 Ppg Timer
CHAPTER 8 PPG TIMER This chapter describes the PPG timer, register configurations and functions, and PPG timer operation. The chapter also provides a block diagram of the PPG timer. 8.1 "Overview of PPG Timer" 8.2 "Block Diagram of PPG Timer" 8.3 "Registers of PPG Timer"...
Page 216: Overview Of Ppg Timer
CHAPTER 8 PPG TIMER Overview of PPG Timer The PPG timer can generate PWM waveforms with great precision and efficiency. The MB91150 has six built-in channels for the PPG timers. Each channel consists of the following elements: • 16-bit down counter •...
Page 217: Block Diagram Of Ppg Timer
CHAPTER 8 PPG TIMER Block Diagram of PPG Timer Figure 8.2-1 "Block diagram of the entire PPG timer" shows the block diagram of an entire PPG timer. Figure 8.2-2 "Block diagram of one channel of the PPG timer" shows the block diagram of one channel of the PPG timer. I Block diagram of the entire PPG timer Figure 8.2-1 Block diagram of the entire PPG timer TRG input...
Page 218 CHAPTER 8 PPG TIMER I Block diagram of one channel of the PPG timer Figure 8.2-2 Block diagram of one channel of the PPG timer PCSR PDUT Prescaler Load 1/16 16-bit down counter 1/64 PPG mask Start Borrow Peripheral clock PWM output Reverse bit Interrupt...
Page 219: Registers Of Ppg Timer
CHAPTER 8 PPG TIMER Registers of PPG Timer Figure 8.3-1 "Register list of PPG timer" lists the registers of the PPG timer. I Register list of PPG timer Figure 8.3-1 Register list of PPG timer Address General control register 1 00000094 GCN1 General control register 2...
Page 220 CHAPTER 8 PPG TIMER Figure 8.3-1 Register list of PPG timer (continued) 000000B0 Timer register (ch3) PTMR3 000000B2 Cycle set register (ch3) PCSR3 000000B4 Duty set register (ch3) PDUT3 000000B6 Control status register (ch3) PCNH3 PCNL3 00000 0B8 Timer register (ch4) PTMR4 00000 0BA Cycle set register (ch4)
Page 221: Control Status Registers (Pcnh, Pcnl)
CHAPTER 8 PPG TIMER 8.3.1 Control status registers (PCNH, PCNL) The control status register (PCNH, PCNL) controls the PWM timer and indicates the status of the timer. Note that some bits cannot be rewritten while the PWM timer is operating. I Control status registers (PCNH, PCNL) The register configuration of the control status registers is shown below.
Page 222 CHAPTER 8 PPG TIMER [Bit 13] MDSE: Mode selection bit This bit determines whether the PWM operation in which pulses are generated continuously or the one-shot operation in which only single pulses are generated is used. PWM operation (initial value) One-shot operation [Bit 12] RTRG: Restart enable bit This bit determines whether restart through a software trigger or trigger input is allowed.
Page 223 CHAPTER 8 PPG TIMER [Bits 7, 6] EGS1, EGS0: Trigger input edge selection bit This bit selects the valid edge for the activation source selected by the general control register 1. When the software trigger bit is set to 1, a software trigger is enabled regardless of the mode selected.
Page 224 CHAPTER 8 PPG TIMER [Bit 0] OSEL: PWM output polarity specification bit This bit specifies the polarity of the PWM output This bit and bit 9 are combined to select the type of PWM output PMGS OSEL PWM output Normal polarity (initial value) Reverse polarity Fixed to low level Fixed to high level...
Page 225: Pwm Cycle Set Register (Pcsr)
CHAPTER 8 PPG TIMER 8.3.2 PWM cycle set register (PCSR) The PCSR is a register for setting cycles. It has a buffer. Transfers from the buffer are performed through counter borrows. I PWM cycle set register (PCSR) The register configuration of the PCSR is shown below. PCSR Address: ch0 00009A ch1 0000A2...
Page 226: Pwm Duty Set Register (Pdut)
CHAPTER 8 PPG TIMER 8.3.3 PWM duty set register (PDUT) The PDUT is a register for setting duties. It has a buffer. Transfers from the buffer are performed through counter borrows. I PWM duty set register (PDUT) The register configuration of the PDUT is shown below. PDUT Address: ch0 00009C ch1 0000A4...
Page 227: Pwm Timer Register (Ptwr)
CHAPTER 8 PPG TIMER 8.3.4 PWM timer register (PTWR) The PTWR can be used to read the 16-bit down counter. I PWM timer register (PTMR) The register configuration of the PTWR (PTMR) is shown below. PTMR Address: ch0 000098 ch1 0000A0 ch2 0000A8 ch3 0000B0 ch4 0000B8...
Page 228: General Control Register 1 (Gcn1)
CHAPTER 8 PPG TIMER 8.3.5 General control register 1 (GCN1) The GCN1 selects the source of the PWM timer trigger input. Only channels 0-3 can be selected by this register. Channels 4-5 are dedicated to external trigger pins. I General control register 1 (GCN1) The register configuration of the GCN1 is shown below.
Page 229 CHAPTER 8 PPG TIMER [Bits 11-8] TSEL23-20: ch2 trigger input selection bit TSEL23-20 ch2 trigger input EN0 bit of GCN2 EN1 bit of GCN2 EN2 bit of GCN2 (initial value) EN3 bit of GCN2 16-bit reload timer ch0 16-bit reload timer ch1 Setting prohibited External TRG0 External TRG1...
Page 230 CHAPTER 8 PPG TIMER [Bits 3-0] TSEL03-00: ch0 trigger input selection bit TSEL03-00 ch0 trigger input EN0 bit of GCN2 (initial value) EN1 bit of GCN2 EN2 bit of GCN2 EN3 bit of GCN2 16-bit reload timer ch0 16-bit reload timer ch1 Setting prohibited External TRG0 External TRG1...
Page 231: General Control Register 2 (Gcn2)
CHAPTER 8 PPG TIMER 8.3.6 General control register 2 (GCN2) The GCN2 activates a start trigger through software. I General control register 2 (GCN2) The register configuration of the GCN2 is shown below. GCN2 Address: 000097 Attribute Initial value When one of the EN-bits of this register is selected by the GCN1, the register value is passed to the trigger input of the PWM timer.
Page 232: Pwm Operation
CHAPTER 8 PPG TIMER PWM Operation The PWM operation allows continuous pulses to be output after a start trigger is detected. The cycle and duty ratio of the output pulses can be controlled by changing the values of the PCSR and PDUT, respectively. I PWM operation ❍...
Page 233 CHAPTER 8 PPG TIMER ❍ When restart is enabled Figure 8.4-2 "Timing chart of PWM operation (trigger restart enabled)" shows the timing chart of the PWM operation when trigger restart is enabled. Figure 8.4-2 Timing chart of PWM operation (trigger restart enabled) Rising edge detected Restarted by trigger Start...
Page 234: One-Shot Operation
CHAPTER 8 PPG TIMER One-shot Operation The one-shot operation allows output of a single pulse of any width through a trigger. If restart is enabled, the counter value is reloaded when the edge is detected during operation. I One-shot operation ❍...
Page 235 CHAPTER 8 PPG TIMER ❍ When restart is enabled Figure 8.5-2 "Timing chart of one-shot operation (trigger restart enabled)" shows the timing chart of a one-shot operation when a trigger restart is enabled. Figure 8.5-2 Timing chart of one-shot operation (trigger restart enabled) Rising edge detected Restarted by trigger Start...
Page 236: Pwm Timer Interrupt Source And Timing Chart
CHAPTER 8 PPG TIMER PWM Timer Interrupt Source and Timing Chart This section describes interrupt sources and provides the related timing charts. I Interrupt sources and timing chart (PWM output: normal polarity) Figure 8.6-1 "PWM timer interrupt sources and timing chart (PWM output: normal polarity)" shows the PWM timer interrupt sources and a timing chart.
Page 237 CHAPTER 8 PPG TIMER ❍ Example of setting PWM output to all-high level Figure 8.6-3 "Example of setting PWM output to all-high" shows an example of setting PWM output to all-high level. Figure 8.6-3 Example of setting PWM output to all-high Increase duty ratio in stages.
Page 238: Activating Multiple Channels By Using The General Control Register (Gcn)
CHAPTER 8 PPG TIMER Activating Multiple Channels by Using the General Control Register (GCN) You can activate multiple channels at the same time by selecting the start trigger with the GCN. This section shows an example of how GCN2 is set to activate channels via software. I Activating multiple channels with the GCN [Setting procedure] 1) Set the cycle in the PCSR.
Page 239 CHAPTER 8 PPG TIMER I When the 16-bit reload timer is used for activation Specify the 16-bit reload timer as a source in GCN1 (see 3) above). Start the 16-bit reload timer instead of writing data to GCN2 as in 5) above. In addition, set the control status register as follows: •...
Page 240 CHAPTER 8 PPG TIMER...
Page 241: Chapter 9 Multifunctional Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER This chapter gives an overview of the multifunctional timer, the configuration and functions of its registers, and its operation. 9.1 "Overview of Multifunctional Timer" 9.2 "Block Diagram of the Multifunctional Timer" 9.3 "Registers of Multifunctional Timer" 9.4 "Operations of multifunctional timer"...
Page 242: Overview Of Multifunctional Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER Overview of Multifunctional Timer The multifunctional timer consists of the following elements: • 16-bit free-run timer, • eight 16-bit output compares, • eight 16-bit output compares, • 16-bit PPG timer with 6 channels. This function enables output of waveforms based on the 16-bit free-run timer, as well as measuring the width of input pulses and the external clock cycle.
Page 243 CHAPTER 9 MULTIFUNCTIONAL TIMER • Four input captures can operate independently. • Interrupts can be generated by the significant edge of an external input signal. ❍ 16-bit PPG timer (x6) See CHAPTER 8 "PPG Timer".
Page 244: Block Diagram Of The Multifunctional Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER Block Diagram of the Multifunctional Timer Figure 9.2-1 "Block diagram of multifunctional timer" shows a block diagram of the multifunctional timer unit. I Block diagram of multifunctional timer Figure 9.2-1 Block diagram of multifunctional timer Interrupt IVFE STOP MODE SCLR CLK2...
Page 245: Registers Of Multifunctional Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER Registers of Multifunctional Timer This section lists the registers of the multifunctional timer unit. I Registers of multifunctional timer See APPENDIX A "I/O Map", for a list of registers of the multifunctional timer unit.
Page 246: Registers Of 16-Bit Free-Run Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.1 Registers of 16-bit Free-run Timer The 16-bit free-run timer has the following three registers. • Data register (TCDT) • Compare clear register • Timer control status register (TCCS) I Data register (TCDT) The register configuration of the data register (TCDT) is as follows: Bit15 Bit14 Bit13...
Page 247 CHAPTER 9 MULTIFUNCTIONAL TIMER I Timer control status register (TCCS) The register configuration of the timer control register (TCCS) is as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Upper 8 bits of timer ECLK control register Bit7 Bit6 Bit5 Bit4 Bit3...
Page 248 CHAPTER 9 MULTIFUNCTIONAL TIMER [Bit 5]: STOP This bit is used to stop the counter of the 16-bit free-run timer. When the bit is set to 1, the counter of the timer is stopped. When the bit is set to 0, the counter of the timer is started. Allows counting (operation) (initial value) Prohibits counting (stop) Note:...
Page 249 CHAPTER 9 MULTIFUNCTIONAL TIMER [Bits 2, 1, and 0]: CLK2, CLK1, and CLK0 These bits are used to select a counter clock for the 16-bit free-run timer. Immediately after these bits are set to a new value, the clock is switched. Therefore, change these bits while the output compare and input capture are stopped.
Page 250: Registers Of The Output Compare
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.2 Registers of the Output Compare The output compare has the following two registers. • Compare register (OCCP0-7) • Output control register (OCS0-7) I Compare register (OCCP0 to 7) The register configuration of the compare registers (OCCP0 to 7) is as follows: Bit15 Bit14 Bit13...
Page 251 CHAPTER 9 MULTIFUNCTIONAL TIMER [Bit 12]: CMOD If pin output is allowed (OTE1 = 0 or OTE0 = 1), the pin output level reverse operation mode is switched when a compare match is detected. • When CMOD = 0 (initial value), the output level of the pin corresponding to a compare register is reversed.
Page 252 CHAPTER 9 MULTIFUNCTIONAL TIMER [Bits 5 and 4]: IOE1 and IOE0 These bits are used to allow an interrupt of the output compare. An output-compare interrupt occurs when these bits are set to 1 and the interrupt flags (IOP1 and IOP0) are also set to 1. Prohibits output-compare interrupts.
Page 253: Registers Of Input Capture
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.3 Registers of Input Capture The input capture has the following two data registers: • Input capture data register (IPCP0 to 3) • Input capture control register (IPCP) I Input capture data register (IPCP0 to 3) The register configuration of the input capture data registers (IPCP0 to 3) is as follows: Bit15 Bit14...
Page 254 CHAPTER 9 MULTIFUNCTIONAL TIMER [Bits 13, 12, 5 and 4]: ICE3, ICE2, ICE1, and ICE0 These bits are used as input-capture interrupt permission bits. When these bits are set to 1 and the interrupt flags (ICP3, ICP2, ICP1, and ICP0) are also 1, an input-capture interrupt occurs.
Page 255: Operations Of Multifunctional Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER Operations of Multifunctional Timer This section describes the operations of the multifunctional timer. I Explanation of multifunctional timer operation ❍ 16-bit free-run timer The 16-bit free-run timer starts counting from the counter value 0000 after releasing reset. This counter value is the reference time for the 16-bit output compare and 16-bit input capture.
Page 256: Operation Of 16-Bit Free-Run Timer
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.1 Operation of 16-bit Free-run Timer The 16-bit free-run timer starts counting from the counter value 0000 after releasing reset. The counter value becomes the reference time of the 16-bit output compare and the 16-bit input capture. I Explanation of 16-bit free-run timer operation The counter value is cleared under the following conditions.
Page 257 CHAPTER 9 MULTIFUNCTIONAL TIMER Figure 9.4-2 Clearing the counter when the counter value matches that of the compare clear register Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset Compare register Interrupt I Timing to clear the 16-bit free-run timer The counter is cleared by reset, software, or when the counter value matches that of the compare clear register.
Page 258: Operation Of 16-Bit Output Compare
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.2 Operation of 16-bit Output Compare The 16-bit output compare compares the set compare register value with the value of the 16-bit free-run timer. If the values match, the compare can set an interrupt flag and reverse the output level.
Page 259 CHAPTER 9 MULTIFUNCTIONAL TIMER Figure 9.4-6 Example of the output waveform when compare registers 0 and 1 are used (At the beginning of output, 0 is assumed.) Counter value FFFFh BFFFh 7FFFh 3FFFh 0000h Time Reset Compare register BFFFh Compare register 7FFFh R T 0 0 R T 0 1...
Page 260 CHAPTER 9 MULTIFUNCTIONAL TIMER I Timing of 16-bit output compare The output level can be changed by using two pairs of compare registers. (One when CMOD = The output compare can generate a compare match signal to reverse output and also generate an interrupt when the value of the free-run timer matches that of the set compare register.
Page 261: Operation Of 16-Bit Input Capture
CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.3 Operation of 16-bit Input Capture When the set significant edge is detected, the 16-bit input capture can capture the 16- bit free-run timer value to the capture register to generate an interrupt. I Operation of 16-bit input capture Figure 9.4-8 "Example of capture timing for the input capture"...
Page 262 CHAPTER 9 MULTIFUNCTIONAL TIMER I Input timing of 16-bit input capture Figure 9.4-9 "Input timing of 16-bit input capture" shows the input timing of the 16-bit input capture. Figure 9.4-9 Input timing of 16-bit input capture Counter value N + 1 Input capture input Significant edge Capture signal...
Page 263: Chapter 10 External Interrupt Control Block
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK This chapter gives an overview of the external interrupt control block, the structure and functions of the registers, and the operation of the external interrupt control block. 10.1 "Overview of External Interrupt" 10.2 "External Interrupt Registers" 10.3 "External Interrupt Operation"...
Page 264: Overview Of External Interrupt
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.1 Overview of External Interrupt The external interrupt control block is a block that controls external interrupt requests received through INT0-15. You can select one of the following request levels to be detected: high, low, rising edge, or falling edge.
Page 265: External Interrupt Registers
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2 External Interrupt Registers Figure 10.2-1 "List of external interrupt registers" lists the registers in the external interrupt control block. I List of external interrupt registers Figure 10.2-1 List of external interrupt registers Enable interrupt register (ENIR) External-interrupt request register (EIRR) External level register (ELVR) LB 7...
Page 266: Enable Interrupt Register (Enirn)
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.1 Enable Interrupt Register (ENIRn) The enable interrupt register (ENIRn) masks external interrupt request output. I Enable interrupt register (ENIRn: ENable Interrupt Register n) The register configuration of the enable interrupt register (ENIRn) is shown below. ENI R 0 Initial value Ad d re ss :0 0 0 0C 9...
Page 267: External Interrupt Request Register (Eirrn)
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.2 External Interrupt Request Register (EIRRn) During a read operation, the external interrupt request register (EIRRn) indicates whether a corresponding external interrupt request exists. A write operation clears the value in the flip-flop indicating the request. I External interrupt request register (EIRRn: External Interrupt Request Register n) The register configuration of the external interrupt request register (EIRRn) is shown below.
Page 268: External Interrupt Level Setting Register (Elvr: External Level Register)
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.3 External Interrupt Level Setting Register (ELVR: External Level Register) The external level register (ELVR) selects the level at which an interrupt request is detected. I External level register (ELVR: External Level Register) The register configuration of the external level register is shown below. ELVR 0 Initial value Address:0000CC...
Page 269: External Interrupt Operation
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.3 External Interrupt Operation When the request specified by the ELVR register is input after the request level and enable register are set, this module issues an interrupt request signal to the interrupt controller. I External interrupt operation When the interrupt issued from this resource has the highest priority of all the interrupts issued concurrently in the interrupt controller, the appropriate interrupt is generated.
Page 270: External Interrupt Request Level
CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.4 External Interrupt Request Level When the request level is the edge request, a minimum of three machine cycles (peripheral clock machine cycles) are required for edge detection. When the request input level is in accordance with the level setting, even if the request input previously issued externally is canceled, the request to the interrupt controller remains active because the internal source-holding circuit retains it.
Page 271: Chapter 11 Delayed Interrupt Module
CHAPTER 11 DELAYED INTERRUPT MODULE This chapter gives an overview of the delayed interrupt module, the structure and functions of the registers, and the operation of the delayed interrupt module. 11.1 "Overview of Delayed Interrupt Module" 11.2 "Delayed Interrupt Control Register (DICR)" 11.3 "Operation of Delayed Interrupt Module"...
Page 272: Overview Of Delayed Interrupt Module
CHAPTER 11 DELAYED INTERRUPT MODULE 11.1 Overview of Delayed Interrupt Module The delayed interrupt module issues an interrupt for switching tasks. This module can be used to issue or cancel an interrupt request to the CPU via software. I Block diagram of the delayed interrupt module A block diagram of the delayed interrupt module is shown in Section 12.2 "Block Diagram of the Interrupt Controller".
Page 273: Delayed Interrupt Control Register (Dicr)
CHAPTER 11 DELAYED INTERRUPT MODULE 11.2 Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) controls delayed interrupts. I Delayed interrupt control register (DICR) The register configuration of the delayed interrupt control register is shown below. bit7 (Initial value) DLYI -------0 [Bit0] DLYI...
Page 274: Operation Of Delayed Interrupt Module
CHAPTER 11 DELAYED INTERRUPT MODULE 11.3 Operation of Delayed Interrupt Module The delayed interrupt function issues interrupts for switching tasks. This function can be used to issue or cancel an interrupt request to the CPU via software. I Interrupt number The delayed interrupt is assigned to the interrupt source corresponding to the maximum interrupt number.
Page 275: Chapter 12 Interrupt Controller
CHAPTER 12 INTERRUPT CONTROLLER This chapter provides an overview of the interrupt controller, the structure and functions of the registers, the operation of the interrupt controller. 12.1 "Overview of Interrupt Controller" 12.2 "Block Diagram of the Interrupt Controller" 12.3 "List of Interrupt Controller Registers" 12.4 "Priority Evaluation"...
Page 276: Overview Of Interrupt Controller
CHAPTER 12 INTERRUPT CONTROLLER 12.1 Overview of Interrupt Controller The interrupt controller accepts and arbitrates interrupts. I Hardware configuration of interrupt controller This module consists of the following components. • ICR register • Interrupt priority evaluation circuit • Interrupt level and interrupt number (vector) generator •...
Page 277: Block Diagram Of The Interrupt Controller
CHAPTER 12 INTERRUPT CONTROLLER 12.2 Block Diagram of the Interrupt Controller Figure 12.2-1 "Block diagram of the interrupt controller" shows a block diagram of the interrupt controller. I Block diagram of the interrupt controller Figure 12.2-1 Block diagram of the interrupt controller INTO Priority evaluation NMI handling...
Page 278: List Of Interrupt Controller Registers
CHAPTER 12 INTERRUPT CONTROLLER 12.3 List of Interrupt Controller Registers Figure 12.3-1 "List of interrupt controller registers" lists the registers of the interrupt controller. I List of interrupt controller registers Figure 12.3-1 List of interrupt controller registers Address : 00000400 ICR3 ICR2 ICR1...
Page 279 CHAPTER 12 INTERRUPT CONTROLLER Figure 12.3-1 List of interrupt controller registers (Continued) I C R 3 2 Address : 00000420 ICR3 ICR2 ICR1 ICR0 Address : 00000421 I C R 3 3 ICR3 ICR2 ICR1 ICR0 I C R 3 4 Address : 00000422 ICR3 ICR2...
Page 280: Interrupt Control Register (Icr)
CHAPTER 12 INTERRUPT CONTROLLER 12.3.1 Interrupt Control Register (ICR) This register controls interrupts. One of these registers exists for each interrupt input and is used to set the interrupt level of the corresponding interrupt request. I Interrupt control register (ICR) The register configuration of the interrupt control register (ICR) is shown below.
Page 281 CHAPTER 12 INTERRUPT CONTROLLER Table 12.3-1 Interrupt-level setting bits and corresponding interrupt levels ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level Reserved by the system (NMI) Highest level that can be set (High) (Low) Interrupt disabled Since ICR4 is fixed by the system, this register does not have an ICR4 bit.
Page 282: Hold-Request Cancellation-Request Level-Set Register (Hrcl)
CHAPTER 12 INTERRUPT CONTROLLER 12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) This register sets the level for issuing hold-request cancellation requests. I Hold-request cancellation request level set register (HRCL) The register configuration of the hold-request cancellation-request level-set register (HRCL) is shown below. bit7 LVL3 LVL2...
Page 283: Priority Evaluation
CHAPTER 12 INTERRUPT CONTROLLER 12.4 Priority Evaluation This module selects the interrupt source with the highest priority, out of all interrupt sources that occur at the same time, and outputs the interrupt level and interrupt number of the source to the CPU. I Priority evaluation The criteria for evaluating the priority are shown below.
Page 284 CHAPTER 12 INTERRUPT CONTROLLER Table 12.4-1 Relationship between interrupt sources, interrupt numbers, and interrupt levels (Continued) Interrupt source Interrupt number Interrupt Offset TBR default level address Decimal Hexadecimal UART3 (Sending completed) ICR18 000FFF74 DMAC (Exit and error) ICR20 000FFF6C Reload timer 0 ICR21 000FFF68 Reload timer 1...
Page 285: Return From Standby (Stop Or Sleep) Mode
CHAPTER 12 INTERRUPT CONTROLLER 12.5 Return from Standby (Stop or Sleep) Mode This module implements the function that enables a return from the stop mode through interrupts. Return from Standby (Stop or Sleep) Mode. I Return from standby (stop or sleep) mode If at least one interrupt request is issued from a peripheral, the request for returning from the stop mode is sent to the clock control block.
Page 286: Hold-Request Cancellation Request
CHAPTER 12 INTERRUPT CONTROLLER 12.6 Hold-Request Cancellation Request To handle an interrupt with a higher priority while the CPU is in hold status, the requester of the hold request must cancel that request. The interrupt level used to determine whether a hold-request cancellation request is issued needs to be set in the HRCL register.
Page 287: Example Of Using Hold-Request Cancellation-Request Function (Hrcr)
CHAPTER 12 INTERRUPT CONTROLLER 12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) To let the CPU perform an operation with a higher priority during DMA transfer, the DMA must release the hold state by canceling the hold request. In this case, use an interrupt to cause the DMA to cancel the hold request.
Page 288 CHAPTER 12 INTERRUPT CONTROLLER I Hold-request cancellation-request sequence ❍ Example for the interrupt routine Figure 12.7-2 "Sample timing chart of the hold request cancellation-request sequence (Interrupt level is HRCL > a)" is a sample timing chart of the hold request cancellation-request sequence (interrupt level HRCL >...
Page 289 CHAPTER 12 INTERRUPT CONTROLLER Sample interrupt routine (1) PDRR incremented (2) Interrupt source cleared (3) PDRR decremented (4) RETI When an interrupt request is issued, the interrupt level is changed. If this level is higher than the level specified in the HRCL register, the HRCR is activated for the DMA. This causes the DMA to cancel the hold request.
Page 290 CHAPTER 12 INTERRUPT CONTROLLER Sample interrupt routine (1), (5) Increment PDRR. (2), (6) Clear the interrupt source. (3), (7) Decrement PDRR. (4), (8) RETI In this example, an interrupt with a higher priority occurs while interrupt routine I is running. This example also prevents a hold request from being issued accidentally by incrementing the PDRR at the beginning of each interrupt routine and decrementing the PDRR at the end.
Page 291: Chapter 13 8/10-Bit A/D Converter
CHAPTER 13 8/10-BIT A/D CONVERTER This chapter provides an overview of the 8/10-bit A/D converter, configuration and functions of its registers, and operation of the 8/10-bit A/D converter. 13.1 "Overview of the 8/10-bit A/D Converter" 13.2 "8/10-bit A/D Converter Block Diagram" 13.3 "8/10-bit A/D Converter Pins"...
Page 292: Overview Of The 8/10-Bit A/D Converter
CHAPTER 13 8/10-BIT A/D CONVERTER 13.1 Overview of the 8/10-bit A/D Converter The 8/10-bit A/D converter converts an analog voltage (input voltage) that is input to an analog input pin into a digital value. The 8/10-bit A/D converter has the following features: I Features of the 8/10-bit A/D converter The 8/10-bit A/D converter changes an analog input voltage into a 10-bit or 8-bit digital value...
Page 293: 8/10-Bit A/D Converter Block Diagram
CHAPTER 13 8/10-BIT A/D CONVERTER 13.2 8/10-bit A/D Converter Block Diagram Figure 13.2-1 "8/10-bit A/D converter block diagram" is a block diagram of the 8/10-bit A/D converter. I 8/10-bit A/D converter block diagram Figure 13.2-1 8/10-bit A/D converter block diagram D/A converter Successive appro -ximation register...
Page 294 CHAPTER 13 8/10-BIT A/D CONVERTER ❍ Decoder Selects the analog input pin to be used in accordance with the setting of the ANE0 to ANE2 bits and ANS0 to ANS2 bits for the A/D control status register (ADCS1). ❍ Analog channel selector Selects one of the eight analog input pins to be used.
Page 295: 8/10-Bit A/D Converter Pins
CHAPTER 13 8/10-BIT A/D CONVERTER 13.3 8/10-bit A/D Converter Pins This section provides a block diagram of the 8/10-bit A/D converter pins. I 8/10-bit A/D converter pins The 8/10-bit A/D converter pins are also used as general-purpose ports. Table 13.3-1 "8/10-bit A/D converter pins"...
Page 296 CHAPTER 13 8/10-BIT A/D CONVERTER 8/10-bit A/D converter pin block diagram Figure 13.3-1 "Block diagram of the pins PK0/AN0 to PK7/AN7" is a block diagram of the 8/10- bit A/D converter pins. Figure 13.3-1 Block diagram of the pins PK0/AN0 to PK7/AN7 AICK Analog input PDR (port data register)
Page 297: 8/10-Bit A/D Converter Registers
CHAPTER 13 8/10-BIT A/D CONVERTER 13.4 8/10-bit A/D Converter Registers Figure 13.4-1 "Schema of the 8/10-bit A/D converter registers" provides a schema of the 8/10-bit A/D converter registers. I Schema of the 8/10-bit A/D converter registers Figure 13.4-1 Schema of the 8/10-bit A/D converter registers 0000EB h AICK 0000E6 h...
Page 298: A/D Control Status Register 1 (Adcs1)
CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.1 A/D Control Status Register 1 (ADCS1) A/D control status register 1 (ADCS1) is used for starting conversion via software, selecting a start trigger, enabling/disabling interrupt requests, checking the state of interrupt requests, and indicating when the converter is temporarily stopped or converting signals.
Page 299 CHAPTER 13 8/10-BIT A/D CONVERTER [Bit 15] BUSY (Bit indicating conversion is in progress) • This is the bit for indicating that the A/D converter is currently performing a conversion. • When a read access shows that this bit is 0, the converter is not executing an A/D conversion.
Page 300 CHAPTER 13 8/10-BIT A/D CONVERTER • In intermittent-conversion mode, this bit cannot restart A/D conversion. (Note) Do not specify forcible stop and start via software (BUSY = 0 and STRT = 1) at the same time. [Bit 8] RESV (Reserved bit) (Note) Be sure to set this bit to 0.
Page 301: A/D Control Status Register 0 (Adcs0)
CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.2 A/D Control Status Register 0 (ADCS0) A/D control status register 0 (ADCS0) is used for selecting a conversion mode and A/D conversion channel. I A/D control status register 0 (ADCS0) Figure 13.4-3 "A/D control status register 0 (ADCS0)" shows the configuration and function outline of A/D Control Status Register 0 (ADCS0).
Page 302 CHAPTER 13 8/10-BIT A/D CONVERTER [Bit 7, 6] MD1, MD0 (A/D conversion mode selection bits) • These bits are used for selecting the A/D conversion mode. • Single-conversion mode 1, single-conversion mode 2, continuous-conversion mode, or intermittent-conversion mode is selected in accordance with the values in the MD1 and MD0 bits.
Page 303: A/D Data Register (Adcr)
CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.3 A/D Data Register (ADCR) The A/D data register (ADCR) stores the result of A/D conversion. This register is also used for selecting the resolution of A/D conversion. I A/D data register (ADCR) The figure below shows the configuration of the A/D data register (ADCR). Figure 13.4-4 A/D data register (ADCR0, 1) bit15 bit14...
Page 304 CHAPTER 13 8/10-BIT A/D CONVERTER [Bit 14, 13] ST1, ST0 (Sampling time setting bits) • These bits are used for selecting the A/D conversion sampling time. • After A/D conversion is started, analog input is acquired for the time specified by these bits. Note: When 00 for 8 MHz is specified when 16-MHz operation is used, analog voltages may not be correctly acquired.
Page 305: 8/10-Bit A/D Converter Interrupt
CHAPTER 13 8/10-BIT A/D CONVERTER 13.5 8/10-bit A/D Converter Interrupt The 8/10-bit A/D converter can generate an interrupt request when data is set in the A/D data register during A/D conversion. I 8/10-bit A/D converter interrupt Table 13.5-1 "8/10-bit A/D converter interrupt control bits and cause for an interrupt" shows the 8/10-bit A/D converter interrupt control bits and the cause for an interrupt.
Page 306: Operation Of The 8/10-Bit A/D Converter
CHAPTER 13 8/10-BIT A/D CONVERTER 13.6 Operation of the 8/10-bit A/D Converter The 8/10-bit A/D converter supports three modes: single-conversion mode, continuous-conversion mode, or intermittent-conversion mode. This section describes the operation of the converter in each mode. I Operation in single-conversion mode In single-conversion mode, analog inputs from channels specified by the ANS bits and ANE bits are converted in sequence.
Page 307 CHAPTER 13 8/10-BIT A/D CONVERTER Figure 13.6-2 Continuous-conversion mode setting bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADCS BUSY INTE PAUS STS1 STS0 STRT ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 served Stores converted data.
Page 308: A/D Converted Data Preservation Function
CHAPTER 13 8/10-BIT A/D CONVERTER 13.7 A/D Converted Data Preservation Function The converted data preservation function is executed when A/D conversion is performed while interrupts are enabled. I A/D converted data preservation function This A/D converter has only one data register for storing converted data. When A/D conversion is performed, data stored in the data register is stored externally and rewritten at the end of conversion.
Page 309: Notes On Using The 8/10-Bit A/D Converter
CHAPTER 13 8/10-BIT A/D CONVERTER 13.8 Notes on Using the 8/10-bit A/D Converter This section provides notes on using the 8/10-bit A/D converter. I Notes on using the 8/10-bit A/D converter ❍ Analog input pin The A/D input pins are also used as I/O pins for port K. The pins are switched using the port K direction register (DDRK) and analog input permission register (AICK).
Page 310 CHAPTER 13 8/10-BIT A/D CONVERTER...
Page 311: Chapter 14 8-Bit D/A Converter
CHAPTER 14 8-BIT D/A CONVERTER This chapter provides an overview of the 8-bit D/A converter, the configuration and functions of the registers, and the operation of the 8-bit D/A converter. 14.1 "Overview of the 8-bit D/A Converter" 14.2 "8-bit D/A Converter Block Diagram" 14.3 "8-bit D/A Converter Registers"...
Page 312: Overview Of The 8-Bit D/A Converter
CHAPTER 14 8-BIT D/A CONVERTER 14.1 Overview of the 8-bit D/A Converter This 8-bit D/A converter supports a resolution of 8 bits and is an R-2R type D/A converter. I Features of the 8-bit D/A converter The MB91150 contains a 3-channel D/A converter. The D/A control registers can control the output of the three channels separately.
Page 313: 8-Bit D/A Converter Block Diagram
CHAPTER 14 8-BIT D/A CONVERTER 14.2 8-bit D/A Converter Block Diagram The 8-bit D/A converter consists of the following three blocks: • 8-bit resistance ladder • Data registers • Control registers I 8-bit D/A converter block diagram Figure 14.2-1 8-bit D/A converter block diagram DA27 DA20 DA17...
Page 314: 8-Bit D/A Converter Registers
CHAPTER 14 8-BIT D/A CONVERTER 14.3 8-bit D/A Converter Registers Figure 14.3-1 "List of the 8-bit D/A converter registers" lists the 8-bit D/A converter registers. I List of the 8-bit D/A converter registers Figure 14.3-1 List of the 8-bit D/A converter registers DADR0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter data register 0...
Page 315: D/A Control Registers (Dacr0, Dacr1, Dacr2)
CHAPTER 14 8-BIT D/A CONVERTER 14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) The D/A control registers (DACR0, DACR1, and DACR2) enable or disable D/A converter output. I D/A control registers (DACR0, DACR1, DACR2) The figure below shows the configuration of the D/A control registers (DACR0, DACR1, DACR2).
Page 316: D/A Data Registers (Dadr2, Dadr1, Dadr0)
CHAPTER 14 8-BIT D/A CONVERTER 14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) The D/A data registers (DADR2, DADR1, and DADR0) specify the D/A converter output voltage. I D/A data registers (DADR2, DADR1, DADR0) The figure below shows the configuration of the D/A data registers (DADR2, DADR1, DADR0). DADR0 Initial value DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00...
Page 317: 8-Bit D/A Converter Operation
CHAPTER 14 8-BIT D/A CONVERTER 14.4 8-bit D/A Converter Operation D/A output starts by setting the desired D/A output value in the D/A data register (DADR) and setting the permission bit for the D/A output channel in the D/A control register (DACR) to 1.
Page 318 CHAPTER 14 8-BIT D/A CONVERTER...
Page 319: Chapter 15 Uart
CHAPTER 15 UART This chapter describes the UART, the configuration and functions of UART registers, and UART operations. 15.1 "Overview of the UART" 15.2 "UART Block Diagram" 15.3 "UART Pins" 15.4 "UART Registers" 15.5 "Interrupts" 15.6 "Receive-Interrupt Generation and Flag Set Timing" 15.7 "Send-Interrupt Generation and Flag Set Timing"...
Page 320: Overview Of The Uart
CHAPTER 15 UART 15.1 Overview of the UART The UART is a general-purpose serial data communication interface for synchronous or asynchronous communication (start-stop synchronization) with external devices. The UART has an ordinary bidirectional communication function (normal mode) and a master/slave-type communication function (multiprocessor mode: Only the master is supported).
Page 321 CHAPTER 15 UART Table 15.1-2 "UART operation modes" lists the UART operation modes. Table 15.1-2 UART operation modes Data length Synchronizatio Operation mode Stop-bit length Without With n method parity parity Normal mode 7 bits or 8 bits Asynchronous 1 bit or 2 bits (*2) Multiprocessor mode 8 + 1 *1 Asynchronous...
Page 322: Uart Block Diagram
CHAPTER 15 UART 15.2 UART Block Diagram Figure 15.2-1 "UART block diagram" shows a block diagram of UART. I UART block diagram Figure 15.2-1 UART block diagram Control bus Receive-interrupt signal #26-29* Dedicated baud-rate generator Send-interrupt signal Send clock Clock 16-bit reload #31-34* selector...
Page 323 CHAPTER 15 UART The following describes the function of each block. ❍ Clock selector The clock selector selects the send and receive clocks from the dedicated baud-rate generator, external input clock, and internal clock (clock supplied from the 16-bit reload timer). ❍...
Page 324: Uart Pins
CHAPTER 15 UART 15.3 UART Pins This section describes the UART pins and provides pin block diagrams. I UART pins UART pins can also be used as general-purpose ports. Table 15.3-1 "UART pins" shows the pin functions, input-output format, and settings for using the UART. Table 15.3-1 UART pins Input- Open-...
Page 325 CHAPTER 15 UART Table 15.3-1 UART pins (Continued) Input- Open- Pull-up Standby Settings necessary for Pin name output drain function selection control using the pins format control Port I input- Set to input port PI0/SIN2 output/serial (DDRI: Bit 0 = 0) data input Port I input- CMOS...
Page 326 CHAPTER 15 UART I UART pin block diagram Figure 15.3-1 "UART pin block diagram" shows a block diagram of UART pins. Figure 15.3-1 UART pin block diagram Data Bus Resource input PDR read Resource output Resource output enabled ODCR PDR : Port Data Register DDR : Data Direction Register ODCR: OpenDrain Control Register PCR : Pull-up Control Register...
Page 327: Uart Registers
CHAPTER 15 UART 15.4 UART Registers Figure 15.4-1 "UART registers" shows the configuration of the UART registers. I UART registers Figure 15.4-1 UART registers Address bit 15 ........bit 8 bit 7 ........bit 0 ch0:0000_001Eh,1Fh ch1:0000_0022h,23h SCR (control register) SMR (mode register) ch2:0000_0026h,27h ch3:0000_002Ah,2Bh ch0:0000_001Ch,1Dh...
Page 328: Control Register (Scr0-3)
CHAPTER 15 UART 15.4.1 Control register (SCR0-3) The control register (SCR0-3) sets the parity, selects the stop-bit length and data length, selects the frame data format in mode 1, clears the receive-error flag, and sets send- and receive-operations to enabled or disabled. I Control register (SCR0-3) The configuration of the control register (SCR0-3) is shown below.
Page 329 CHAPTER 15 UART [Bit 15] PEN (Parity enable bit) This bit selects whether to add a parity bit to serial data (for sending). This bit selects whether to detect a parity bit (for receiving) within the serial data. (Note) When operation mode 1 or 2 is selected, parity cannot be used. Always set this bit to [Bit 14] P (Parity selection bit) This bit selects odd parity or even parity when parity is enabled (PEN = 1).
Page 330: Mode Register (Smr0-3)
CHAPTER 15 UART 15.4.2 Mode register (SMR0-3) The mode register (SMR0-3) selects the operation mode, selects the baud-rate clock, and sets serial data and clock output to pin enabled or disabled. I Mode register (SMR0-3) The configuration of the mode register (SMR0-3) is shown below. Figure 15.4-3 Mode register (SMR0-3) Address bit15 ....
Page 331 CHAPTER 15 UART [Bit 7, 6] MD1, MD0 (Operation mode selection bit) • These bits select the operation mode. In operation mode 1 (multiprocessor mode) these bits can only be used at the side of the master in master-slave-type communication. These bits cannot be used in the slave unit because the UART does not have a function for distinguishing between the address and the data at reception.
Page 332: Status Register (Ssr0-3)
CHAPTER 15 UART 15.4.3 Status register (SSR0-3) The status register (SSR0-3) is used to check the send, receive and error statuses, and sets interrupt enabled or disabled. I Status register (SSR0-4) The configuration of the status register (SSR0-3) is shown below. Figure 15.4-4 Status register (SSR0-3) Address bit15...
Page 333 CHAPTER 15 UART [Bit 14] ORE (Overrun error flag bit) • If an overrun occurs at reception, this bit is set to 1. When the REC bit of the mode register (SMR0-3) is set to 0, this bit is cleared to 0. •...
Page 334: Input-Data Register (Sidr0-3), Output-Data Register (Sodr0-3)
CHAPTER 15 UART 15.4.4 Input-data register (SIDR0-3), output-data register (SODR0-3) The input-data register (SIDR0-3) is for receiving serial data. The output-data register (SODR0-3) is for sending serial data. The SIDR0-3 and SODR0-3 registers are located at the same address. I Input-data register (SIDR0-3) The configuration of the input-data register (SIDR0-3) as shown below.
Page 335 CHAPTER 15 UART the TDRE bit is 1, the next send data can be written. If send-interrupt request output is enabled, a send interrupt occurs. The next send data should be written when a send interrupt occurs or when the TDRE bit is 1. Note: The SODR0-3 is a write-only register and the SIDR0-3 is a read-only register.
Page 336: Communication Prescaler Control Register (Cdcr)
CHAPTER 15 UART 15.4.5 Communication prescaler control register (CDCR) The communication prescaler control register (CDCR) controls division of the machine clock. I Communication prescaler control register (CDCR) The UART operation clock is obtained by dividing the machine clock. This communication prescaler is designed to obtain a fixed baud rate for machine cycles.
Page 337 CHAPTER 15 UART Table 15.4-1 Communication prescaler (Continued) DIV3 DIV2 DIV1 DIV0 Note: After the division ratio has been changed, wait two cycles for the clock to stabilize before performing communication.
Page 338: Interrupts
CHAPTER 15 UART 15.5 Interrupts The UART has receive interrupts and send interrupts. Interrupt requests are generated in the following cases: • When receive data is set in the input-data register (SIDR0-3) or when a receive error occurs • When send data is transferred from the output-data register (SODR0-3) to the send- shift register UART interrupts Table 15.5-1 "UART interrupt control bit and interrupt sources"...
Page 339 CHAPTER 15 UART I UART-related interrupts Table 15.5-2 UART-related interrupts Interrupt control Vector table address register Interrupt Interrupt source number Register TBR default Address Offset name address UART0 receive #26 (1A ICR10 00040A 000FFF94 interrupt UART1 receive #27 (1B ICR11 00040B 000FFF90 interrupt...
Page 340: Receive-Interrupt Generation And Flag Set Timing
CHAPTER 15 UART 15.6 Receive-Interrupt Generation and Flag Set Timing The receive interrupts are interrupts indicating receive completion (SSR0-3: RDRF) and receive-error generation (SSR0-3: PE, ORE, FRE). I Receive-interrupt generation and flag set timing When the stop bit is detected (in operation modes 0 to 4) or when the final bit (D7) of the data is detected (in operation mode 2) during reception, the receive data is stored in input-data register 1 (SIDR0-3).
Page 341: Send-Interrupt Generation And Flag Set Timing
CHAPTER 15 UART 15.7 Send-Interrupt Generation and Flag Set Timing A send interrupt is generated when the output-data register (SODR0-3) enables the next unit of data to be written. I Send-interrupt generation and flag set timing When data from the output-data register (SODR0-3) is transferred to the send-shift register and writing of the next unit of data is enabled, the send data empty flag bit (SSR0-3: TDRE) is set to 1.
Page 342: Baud Rate
CHAPTER 15 UART 15.8 Baud Rate The UART send and receive clocks can be selected from any of the following. • Dedicated baud-rate generator • Internal clock (16-bit reload timer) • External clock (SCK pin input clock) I UART baud-rate selection The baud-rate selection circuit consists of the following.
Page 343 CHAPTER 15 UART I UART Baud-Rate Selection Circuit Figure 15.8-1 "UART baud-rate selection circuit" shows a UART baud rate selection circuit. Figure 15.8-1 UART baud-rate selection circuit SMR0 to 3:CS2/1/0 (Clock selection bit) Clock selector [Dedicated baud-rate generator] For 000b to 101b Divide-by circuit (Synchronous) Prescaler...
Page 344: Baud Rate Based On The Dedicated Baud-Rate Generator
CHAPTER 15 UART 15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator This section shows the baud rates that can be set when the output clock of the dedicated baud-rate generator is selected as the UART transfer clock. I Baud rate based on the dedicated baud-rate generator When the dedicated baud-rate generator is used to generate the transfer clock, the machine clock prescaler is used to divide the machine clock rate by the transfer clock division ratio selected with the clock selector.
Page 345 CHAPTER 15 UART Table 15.8-1 Selection of division ratio based on the machine clock prescaler DIV3 DIV2 DIV1 DIV0 ❍ Synchronous transfer clock division ratio The synchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode register (SMR0-3) as shown in Table 15.8-2 "Selection of synchronous baud-rate division ratio".
Page 346 CHAPTER 15 UART ❍ Asynchronous transfer clock division ratio The asynchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode register (SMR0-4) as shown in Table 15.8-3 "Selection of asynchronous baud-rate division ratio". Table 15.8-3 Selection of asynchronous baud-rate division ratio Synchronous with Equation for SCKI...
Page 347: Baud Rate Based On The Internal Timer (16-Bit Reload Timer 0)
CHAPTER 15 UART 15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) This section shows the settings and equations for calculating the baud rate when the internal clock from 16-bit reload timer 0 is selected as the UART transfer clock. I Baud rate based on the internal timer (16-bit reload timer) When the bits CS2 to CS0 of the mode register (SMR0-3) are set to 110 , the baud rate is...
Page 348 CHAPTER 15 UART ❍ Example of reload-value setting (when the machine clock is 31.9488 MHz) Table 15.8-4 Baud rate and reload value Reload value Asynchronous with the clock (start-stop Synchronous with the clock synchronization) Baud rate X = 2 X = 2 X = 2 X = 2 (Divide-by-two...
Page 349: Baud Rate Based On The External Clock
CHAPTER 15 UART 15.8.3 Baud Rate Based on the External clock This section shows the settings and equations for calculating the baud rate when the external clock is selected as the UART transfer clock. I Baud rate based on the external clock The following three settings are necessary for selecting the baud rate based on the external clock.
Page 350: Uart Operations
CHAPTER 15 UART 15.9 UART Operations The UART has an ordinary bidirectional serial communication function (operation modes 0 and 2) and master/slave-type connection communication function (operation mode 1). I UART operations ❍ Operation mode The UART has three operation modes, mode 0 to mode 2. The inter-CPU connection method and data transfer method can be used to select the operation mode as shown in Table 15.9-1 "UART operation modes".
Page 351 CHAPTER 15 UART ❍ Signal method The UART can handle data in the Non Return to Zero (NRZ) format only. ❍ Operation enable The UART has the TXE (sending) and RXE (receiving) operation enable bits separately for sending and receiving, which are used to control send and receive operations. If operation becomes disabled while the operation is in progress, the following occurs.
Page 352: Operation In Asynchronous Mode (Operation Modes 0 To 1)
CHAPTER 15 UART 15.9.1 Operation in asynchronous mode (operation modes 0 to 1) When the UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the transfer becomes asynchronous. I Operation in asynchronous mode ❍ Transfer-data format Transfer data always starts from the start bit (L level), is transferred LSB first with the specified data bit length, and ends with the stop bit (H level).
Page 353 CHAPTER 15 UART register (SIDR0-3). If an error has occurred, perform the required processing to handle the error. As soon as the receive data is read from SIDR0-3, the RDRF flag is cleared to 0. ❍ Detecting the start bit Implement the following settings to detect the start bit: •...
Page 354 CHAPTER 15 UART • In mode 1, overrun errors and frame errors can be detected, but parity errors cannot be detected. ❍ Parity 0 Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to use parity is specified in the PEN bit of the control register (SCR0-3). Whether to use even-number parity or odd-number parity is specified in the P bit.
Page 355: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 15 UART 15.9.2 Operation in synchronous mode (operation mode 2) When the UART is used in operation mode 2 (normal mode), the transfer mode becomes clock synchronization. I Operation in synchronous mode (operation mode 2) ❍ Transfer-data format In synchronous mode, data is transferred in units of eight bits LSB first without the start bit and stop bit appended.
Page 356 CHAPTER 15 UART ❍ Initialization The setting values of each control register in synchronous mode are shown below. [Mode register (SMR0-3)] - MD1, MD0: 10 - CS2, CS1, CS0: Specify the clock selector clock input. - SCKE: 1 for the dedicated baud-rate generator or internal timer, and 0 for the clock output and external clock (clock input) - SOE: 1 for sending and 0 for receive-only [Control register (SCR0-3)]...
Page 357: Bidirectional Communication Function (Normal Mode)
CHAPTER 15 UART 15.9.3 Bidirectional communication function (normal mode) In operation modes 0 and 2, ordinary serial bidirectional communication can be performed in a one-to-one connection. The synchronization method is asynchronous in operation mode 0 and synchronous in operation mode 2. I Bidirectional communication function To operate the UART in normal mode (operation modes 0 and 2), the settings shown in Figure 15.9-6 "Settings for UART1 operation mode 0"...
Page 358 CHAPTER 15 UART Figure 15.9-8 Example of bidirectional communication flow (Sending side) (Receiving side) Start Start Set operation mode Set operation mode (that (0 or 2) matches the sending side) Send data Set one-byte data in UODR Does receive and perform data exist? communication Read and process...
Page 359: Master/Slave-Type Communication Function (Multiprocessor Mode)
CHAPTER 15 UART 15.9.4 Master/slave-type communication function (multiprocessor mode) The UART can communicate with multiple CPUs in a master/slave-type connection in operation mode 1. However, the UART can only be used as the master CPU. I Master/slave-type communication function To operate the UART in multiprocessor mode (operation mode 1), the settings shown in Figure 15.9-9 "Settings for UART operation mode 1"...
Page 360 CHAPTER 15 UART shown in Table 15.9-2 "Selection of master/slave-type communication functions". Table 15.9-2 Selection of master/slave-type communication functions Operation mode Synchronizati Data Parity Stop bit on method Master CPU Slave CPU A/D=1 Address send and receive 8-bit address Mode 1 None Asynchronous 1 bit or 2 bits...
Page 361: Notes On Using Uart
CHAPTER 15 UART 15.10 Notes on Using UART This section provides notes on using the UART. I Notes on using the UART ❍ Operation enabled The UART has the TXE (sending) and RXE (receiving) operation enable bits in the control register (SCR0-3) separately for sending and receiving.
Page 362 CHAPTER 15 UART...
Page 363 CHAPTER 16 I C INTERFACE This chapter gives an overview of the I C interface, the configuration and functions of registers, and the operation of the I C interface. It also provides the related block diagrams. 16.1 "Overview of I2C Interface" 16.2 "Block Diagrams of I2C Interface"...
Page 364: Chapter 16 I 2 C Interface
CHAPTER 16 I C INTERFACE 16.1 Overview of I C Interface The I C interface is a serial I/O port that supports inter-IC buses. The I C interfaces operate as master/slave devices on the I C bus. I Features of I C interface In the MB91150, the I C interface has one built-in channel.
Page 365: Block Diagram Of I C Interface
CHAPTER 16 I C INTERFACE 16.2 Block Diagram of I C Interface Figure 16.2-1 "Block diagram of I C interface" is a block diagram of the I2C interface. I Block diagram of I C interface Figure 16.2-1 Block diagram of I C interface ICCR C Enable...
Page 366: Registers Of I C Interface
CHAPTER 16 I C INTERFACE 16.3 Registers of I C Interface Figure 16.3-1 "Registers of I C Interface" lists the registers of the I2C interface. I Registers of the I C interface Figure 16.3-1 Registers of I C interface Address Bit15 Bit14 Bit13...
Page 367: Bus Control Register (Ibcr)
CHAPTER 16 I C INTERFACE 16.3.1 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions. • Interrupt request/interrupt enable • Start condition generation • Master/slave selection • Acknowledge enable I Bus control register (IBCR) The bus control register (IBCR) has the following bit configuration. Address Bit15 Bit14...
Page 368 CHAPTER 16 I C INTERFACE [bit 13] SCC (Start Condition Continue) This bit is a start condition generation bit. (During writing) Inapplicable Generates another start condition during transfer to or from the master. The read value of this bit is always 0. [bit 12] MSS (Master Slave Select) This bit is a master/slave selection bit.
Page 369 CHAPTER 16 I C INTERFACE [bit 8] INT (INTerrupt) This bit is a transfer-end interrupt-request flag bit. (During writing) Clears the transfer-end interrupt-request flag. Inapplicable (For Read) Transfer has not completed. When the transfer of 1 byte, including the acknowledge bit, ends, and one of the following conditions is met, this bit is set.
Page 370: Bus Status Register (Ibsr)
CHAPTER 16 I C INTERFACE 16.3.2 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • Detection of repeated start conditions • Detection of Arbitration Lost • Acknowledge storage • Data transfer • Addressing detection • Detection of general call address •...
Page 371 CHAPTER 16 I C INTERFACE This bit is cleared by setting the INT bit to 0 in a write operation. [bit 4] LRB (Last Received Bit) This bit stores Acknowledge. This bit stores an Acknowledge sent from the receiving side. This bit is cleared when a start or stop condition is detected.
Page 372: Address Register (Iadr)/Data Register (Idar)
CHAPTER 16 I C INTERFACE 16.3.3 Address Register (IADR)/Data Register (IDAR) The address register (IADR) is used to specify a slave address. The data register (IADR) is used to perform serial transfer. I Address register (IADR) The address register (IADR) has the following bit configuration: Address Bit15 Bit14...
Page 373: Clock Control Register (Iccr)
CHAPTER 16 I C INTERFACE 16.3.4 Clock Control Register (ICCR) The clock control register (ICCR) has the following functions: • Enabling the I C interface • Setting of serial clock frequency I Clock control register (ICCR) The clock control register (ICCR) has the following bit configuration: Address Bit7 Bit6...
Page 374 CHAPTER 16 I C INTERFACE Table 16.3-1 "Setting of serial clock frequency" lists the m and n values for CS4-CS0. Table 16.3-1 Setting of serial clock frequency...
Page 375: Operation Of I C Interface
CHAPTER 16 I C INTERFACE 16.4 Operation of I C Interface The I C bus establishes communication via two duplex bus lines, one serial data line (SDA) and one serial clock line (SCL). The I C interface has two open-drain input pins (SDA and SCL) to make the wiring possible.
Page 376 CHAPTER 16 I C INTERFACE ❍ Arbitration When more than one master transmits data at the same time, arbitration starts. When the data to be transmit is 1, and the data on the SDA line is at the "L-level", the master sets AL=1, assuming that it has lost the arbitration.
Page 377: Chapter 17 Dma Controller
CHAPTER 17 DMA CONTROLLER This chapter describes the DMA controller, its registers and functions, and its operations. 17.1 "Overview of the DMA Controller Overview" 17.2 "Block Diagram of the DMA Controller" 17.3 "Registers of the DMA Controller" 17.4 "Transfer Modes Supported by the DMA Controller" 17.5 "Transfer-Acceptance Signal Output and Transfer-End Signal Output"...
Page 378: Overview Of The Dma Controller Overview
CHAPTER 17 DMA CONTROLLER 17.1 Overview of the DMA Controller Overview The DMA controller is a module built in the MB91150 that performs DMA (Direct Memory Access) transfers. I Features of the DMA controller • Eight channels • The 3 transfer modes below are available •...
Page 379: Block Diagram Of The Dma Controller
CHAPTER 17 DMA CONTROLLER 17.2 Block Diagram of the DMA Controller Figure 17.2-1 "Block diagram of the DMA controller" shows a block diagram of the DMA controller. I Block diagram of the DMA controller Figure 17.2-1 Block diagram of the DMA controller DACK0-2 Edge/level DREQ0-2...
Page 380: Registers Of The Dma Controller
CHAPTER 17 DMA CONTROLLER 17.3 Registers of the DMA Controller Figure 17.3-1 "Registers for the DMA controller" lists the registers of the DMA controller. I Registers of the DMA controller Figure 17.3-1 Registers for the DMA controller [Internal registers in the DMAC] 00000200 DPDP 00000204...
Page 381: Dmac Parameter Descriptor Pointer (Dpdp)
CHAPTER 17 DMA CONTROLLER 17.3.1 DMAC parameter descriptor pointer (DPDP) This pointer stores the start address in the descriptor table for the DMAC in RAM. Bits 0 to 6 are always set to 0. The start address of the descriptor can be set in units of 128 bytes.
Page 382: Mac Control Status Register (Dacsr)
CHAPTER 17 DMA CONTROLLER 17.3.2 MAC control status register (DACSR) The DMAC control status register (DACSR) is an internal register in the DMAC that controls the entire DMAC and indicates its status. I DMAC control status register (DACSR) The register configuration of the DMAC control status register (DACSR) is given below. 00000204 DER7 DED7...
Page 383 CHAPTER 17 DMA CONTROLLER - Although these bits can be read and written, these bits can only be set to 0. - Read/modify/write instructions always return a reading value of 1. [Bits 29, 25, 21, 17, 13, 9, 5, and 1] DIEn (DMA interrupt enable) Specify whether to generate an interrupt at the end of DMA transfer over channel n (when DEDn is set to 1).
Page 384: Dmac Pin Control Register (Datcr)
CHAPTER 17 DMA CONTROLLER 17.3.3 DMAC pin control register (DATCR) The DMAC pin control register (DATCR) in the DMAC controls an external transfer request input pin, an external transfer-request-acceptance output pin, and an external transfer-end output pin. I DMAC pin control register (DATCR) The register configuration of the DMAC pin control register (DATCR) is given below.
Page 385 CHAPTER 17 DMA CONTROLLER [Bits 19, 11, and 3] AKSEn [Bits 18, 10, and 2] AKDEn Specify the time at which to generate a transfer-request-acceptance output signal. Also, specify whether to enable or disable the function for output of transfer-request-acceptance signals from a pin.
Page 386: Register Of The Descriptor In Ram
CHAPTER 17 DMA CONTROLLER 17.3.4 Register of the descriptor in RAM This register stores information for each channel for DMA transfer. This register has a size of 12 bytes per channel, and uses the memory space at the address allocated by the DPDP. For details on the start address of the descriptor for each channel, see Table 17.3-1 "Descriptor address for each channel".
Page 387 CHAPTER 17 DMA CONTROLLER Transfer source Transfer destination SCS1 SCS0 DCS1 DCS0 address address Address incremented Address incremented Address incremented Address decremented Address incremented Address fixed Address decremented Address incremented Address decremented Address decremented Address decremented Address fixed Address fixed Address incremented Address fixed Address decremented...
Page 388 CHAPTER 17 DMA CONTROLLER [Bits 1 and 0] MOD1 and MOD0 transfer mode Specify transfer mode. MOD1 MOD2 Operating mode Single/block mode Burst mode Continuous transfer mode Disabled Note: Only ch0 to ch2 can use continuous transfer mode. I Second word in the descriptor SADR Stores a transfer source address.
Page 389: Transfer Modes Supported By The Dma Controller
CHAPTER 17 DMA CONTROLLER 17.4 Transfer Modes Supported by the DMA Controller The DMA controller supports the following three transfer modes. • Single/block transfer mode • Continuous transfer mode • Burst transfer mode I Single/block transfer mode 1. Use an initialization routine to set the descriptor. 2.
Page 390 CHAPTER 17 DMA CONTROLLER I Continuous transfer mode 1. Use an initialization routine to set the descriptor. 2. Use the appropriate program to initialize the DMA transfer request source. Set the external transfer request input pin to H or L level detection. 3.
Page 391 CHAPTER 17 DMA CONTROLLER descriptor together with the DMACT value. 8. The bus right is returned to the CPU. 9. DACSR DEDn is set to 1, and a CPU interrupt is generated if interrupts are enabled. If the descriptor is stored in the internal RAM, and data of byte length is transferred between external buses, the required minimum cycle count per transfer is as described below, under the conditions indicated: •...
Page 392: Step Transfer (Single/Block Transfer)
CHAPTER 17 DMA CONTROLLER 17.4.1 Step Transfer (Single/Block Transfer) The step transfer (single/block transfer) performs one DMA transfer per transfer request. Edge or level can be selected for the DREQ input. I Step transfer (single/block transfer) In step transfer mode, the bus access right is transferred to the CPU for each DMA transfer. The unit of transfer unit is determined based on the block size.
Page 393: Continuos Transfer
CHAPTER 17 DMA CONTROLLER 17.4.2 Continuos Transfer In continuos transfer, DMA transfer is performed while a transfer request [DREQ] retains the active level. For the DREQ input, only level sense mode is possible. I Continuous transfer In continuous transfer mode, the bus access right is transferred to the CPU when the transfer count register is reset to 0 or the DREQ input is negated.
Page 394: Burst Transfer
CHAPTER 17 DMA CONTROLLER 17.4.3 Burst Transfer In burst transfer, DMA transfer is performed as many times as specified in a transfer request [DREQ]. Level or edge sense mode can be selected for the DREQ input. I Burst transfer In burst transfer mode, DMA transfer is finished when the transfer count register becomes 0, and bus access right is transferred to the CPU.
Page 395: Differences Because Of Dreq Sense Mode
CHAPTER 17 DMA CONTROLLER 17.4.4 Differences Because of DREQ Sense Mode The DREQ sense modes include level and edge modes. This section provides notes on each mode. I Notes on level mode In level sense mode, be careful that no overrun occurs during DMAC transfer. Negate DREQ until the rising DACK edge during transfer destination access.
Page 396 CHAPTER 17 DMA CONTROLLER I Notes on edge mode In edge sense mode, the next DREQ edge must be input after the clearance point of the DMAC request flag. Any edge input before that point is ignored. To ensure the edge is recognized, a negation interval of min 2tCYC [ns] is required. Input the DREQ, as shown in Figure 17.4-6 "Edge-mode timing", after the falling DACK edge during transfer destination access.
Page 397: Transfer-Acceptance Signal Output And Transfer-End Signal Output
CHAPTER 17 DMA CONTROLLER 17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output Channels 0, 1 and 2 support a function for outputting the transfer-request-acceptance signal from a pin. When accepting transfer request input from a pin for DMA transfer, the DMAC outputs the transfer-request-acceptance signal.
Page 398: Notes On The Dma Controller
CHAPTER 17 DMA CONTROLLER 17.6 Notes on the DMA Controller This section provides notes on using the DMA controller. I Priority of channels Once the DMAC is activated by a DMA transfer request over a channel, a DMA transfer request over another channel is not accepted and is held until the end of the current transfer.
Page 399 CHAPTER 17 DMA CONTROLLER with 0. I DMA transfer operation in sleep mode DMA transfer operation can not use during sleep state. Before the CPU changes to sleep state, the state of DMA transfer operation must be set to prohibition state. I Transfer operation to DMAC internal register Do not specify a DMAC internal register as a transfer destination address.
Page 400: Timing Charts For The Dma Controller
CHAPTER 17 DMA CONTROLLER 17.7 Timing Charts for the DMA Controller This section covers timing charts for DMA controller operation. • Timing chart for the descriptor access section • Timing chart for the data transfer section • Timing chart for transfer termination in continuous transfer mode •...
Page 401: Timing Charts For The Descriptor Access Section
CHAPTER 17 DMA CONTROLLER 17.7.1 Timing charts for the descriptor access section This section covers the timing charts for the descriptor access section. I Descriptor access section ❍ Request pin input mode: Level, Descriptor address: External DREQn Addr pin Data pin DACK DEOP ❍...
Page 402 CHAPTER 17 DMA CONTROLLER ❍ Request pin input mode: Edge, Descriptor address: External DREQn Addr pin Data pin DACK DEOP ❍ Request input mode: Edge, Descriptor address: Internal DREQn Addr pin Data pin DACK DEOP Note: For the part from DREQn generation to the start of DMAC operation, only the conditions for the fastest case are covered.
Page 403: Timing Charts For The Data Transfer Section
CHAPTER 17 DMA CONTROLLER 17.7.2 Timing charts for the data transfer section This section covers timing charts for the data transfer section. I Data transfer section, 16/8-bit data ❍ Transfer source area: External, Transfer destination area: External DREQn Addr pin Data pin DACK DEOP...
Page 404 CHAPTER 17 DMA CONTROLLER ❍ Transfer source area: Internal RAM, Transfer destination area: External DREQn Addr pin Data pin DACK DEOP...
Page 405: Timing Charts For Transfer Termination In Continuous Transfer Mode
CHAPTER 17 DMA CONTROLLER 17.7.3 Timing charts for transfer termination in continuous transfer mode This section covers timing charts for transfer termination in continuous transfer mode. I Transfer termination in continuous transfer mode (when either address is fixed), 16/8-bit data ❍...
Page 406 CHAPTER 17 DMA CONTROLLER I Transfer termination in continuous transfer mode (when both addresses are changed), 16/8-bit data ❍ Transfer source area: External, Transfer destination area: External DREQn Addr pin Data pin DACK DEOP ❍ Transfer source area: External, Transfer destination area: Internal RAM DREQn Addr pin Data pin...
Page 407: Timing Charts For The Transfer Termination Operation
CHAPTER 17 DMA CONTROLLER 17.7.4 Timing charts for the transfer termination operation This section covers timing charts for the transfer termination operation. I Transfer termination operation (when either address is fixed) ❍ Bus width: 16 bits, Data length: 8/16 bits Addr pin #1/2H #1/2L...
Page 408 CHAPTER 17 DMA CONTROLLER I Transfer termination operation (when both addresses are changed) ❍ Bus width: 16 bits, Data length: 8/16 bits Addr pin Data pin AKSE = 1 DACK AKDE = 1 Both = 1 EPSE = 1 DEOP EPDE = 1 Both = 1 ❍...
Page 409: Chapter 18 Bit-Search Module
CHAPTER 18 BIT-SEARCH MODULE This chapter describes the bit-search module, the register configuration and functions, and the operation of the bit-search module. 18.1 "Overview of the Bit-Search Module" 18.2 "Registers of the Bit-Search Module" 18.3 "Operation of the Bit-Search Module"...
Page 410: Overview Of The Bit-Search Module
CHAPTER 18 BIT-SEARCH MODULE 18.1 Overview of the Bit-Search Module This module searches for 0 or 1, or for changes in bit values in response to data loaded into the input register, and returns the bit position at which the respective behavior was detected.
Page 411: Registers Of The Bit-Search Module
CHAPTER 18 BIT-SEARCH MODULE 18.2 Registers of the Bit-Search Module The bit-search module registers include the following four: • 0-detection data register (BSD0) • 1-detection data register (BSD1) • Value-change detection register (BSDC) • Detection result register (BSRR) I 0 detection data register (BSD0) The register configuration of the 0 detection data register (BSD0) is given below.
Page 412 CHAPTER 18 BIT-SEARCH MODULE ❍ Writing 1 detection is performed for a written value. ❍ Reading Data storing the internal status of the bit-search module is read. This function is used to save and return the original status when e.g. the interrupt handler uses the bit-search module. The original status can be saved and returned based on the 1 detection data register even if data has been loaded into the 0 detection or value change detection data register.
Page 413: Operation Of The Bit-Search Module
CHAPTER 18 BIT-SEARCH MODULE 18.3 Operation of the Bit-Search Module The bit-search module perform the following operations: • 0 detection • 1 detection • value change detection I 0 detection Data loaded in the 0 detection data register is scanned from the MSB to the LSB, and the position at which the first 0 is detected is returned.
Page 414 CHAPTER 18 BIT-SEARCH MODULE register. Table 18.3-1 "Bit positions and return values (Decimal)" shows the positions of detection and their corresponding return values. If no value change occurred, a value of 32 is returned. During value change detection, the value 0 is not returned as result. [Example of execution] Written data Read value (In decimal notation)
Page 415: Chapter 19 Peripheral Stop Control
CHAPTER 19 PERIPHERAL STOP CONTROL This chapter provides an overview of peripheral stop control and explains the configuration and the function of registers. 19.1 "Overview of Peripheral Stop Control" 19.2 "Peripheral Stop Control Register"...
Page 416: Overview Of Peripheral Stop Control
CHAPTER 19 PERIPHERAL STOP CONTROL 19.1 Overview of Peripheral Stop Control The peripheral stop control stops the clocks for unused resources, which reduces power consumption. I Peripheral stop control registers Figure 19.1-1 "Peripheral stop control registers" lists the peripheral stop control registers. Figure 19.1-1 Peripheral stop control registers ………………...
Page 417: Peripheral Stop Control Registers
CHAPTER 19 PERIPHERAL STOP CONTROL 19.2 Peripheral Stop Control Registers The peripheral stop control registers include the following three: • Stop control register 0 (STPR0) • Stop control register 1 (STPR1) • Stop control register 2 (STPR2) I Stop control register 0 (STPR0) Stop control register 0 (STPR0) has the following bit configuration: Address bit7...
Page 418 CHAPTER 19 PERIPHERAL STOP CONTROL I Stop control register 1 (STPR1) Stop control register 1 (STPR1) has the following bit configuration: Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000091 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 00000000 (R/W)
Page 419 CHAPTER 19 PERIPHERAL STOP CONTROL I Stop control register 2 (STPR2) Stop control register 2 (STPR2) has the following bit configuration: Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ST27 ST26 ST25 ST24 ST23 ST22 000092 000000- - (R/W) [bit 7] ST27 0: Enables PPG0 operation.
Page 420 CHAPTER 19 PERIPHERAL STOP CONTROL...
Page 421: Chapter 20 Calendar Macros
CHAPTER 20 CALENDAR MACROS This chapter provides an overview of the calendar macros, explains the configuration and functions of registers, and the operation of calendar macros. 20.1 "Overview of Calendar Macros" 20.2 "Registers of Calendar Macros" 20.3 "Operation of Calendar Macros"...
Page 422: Overview Of Calendar Macros
CHAPTER 20 CALENDAR MACROS 20.1 Overview of Calendar Macros The calendar macros use a basic clock frequency of 32.768 kHz. These macros have clock functions for years, months, days, hours, minutes, seconds, days of the week, and leap years. For the year, the lower 2 digits of the year, 0 to 99, are counted. I Block diagram of calendar macros Figure 20.1-1 "Block diagram of calendar macros"...
Page 423: Calendar Macro Registers
CHAPTER 20 CALENDAR MACROS 20.2 Calendar Macro Registers The calendar macro registers include the following nine: • Calendar block read/write control register (CAC) • Second data register) (CA1) • Minute data register) (CA2) • Hour data register) (CA3) • Day data register (CA4) •...
Page 424 CHAPTER 20 CALENDAR MACROS I Second data register (CA1) The second data register (CA1) has the following bit configuration: Initial value 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit --XXXXXX [R/W] [bit 7, 6] Reserved These bits are reserved.
Page 425 CHAPTER 20 CALENDAR MACROS I Day data register (CA4) The day data register (CA4) has the following bit configuration: Initial value 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit ---XXXXX [R/W] [bit 7 to 5] Reserved These bits are reserved.
Page 426 CHAPTER 20 CALENDAR MACROS I Year data register (CA7) The year data register (CA7) has the following bit configuration: Initial value 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit -XXXXXXX [R/W] [bit 7] Reserved These bits are reserved.
Page 427: Calendar Macro Operation
CHAPTER 20 CALENDAR MACROS 20.3 Calendar Macro Operation This section describes the reset of calendar macros for initialization and explains how to set and read calendar values. I Initialization reset Only the CAC and CAS registers can be initialized by a normal reset (CPU reset signal, such as reset by TST pin).
Page 428 CHAPTER 20 CALENDAR MACROS...
Page 429: Chapter 21 Flash Memory
CHAPTER 21 FLASH MEMORY This chapter describes the flash memory of this device, its operation, as well as the configuration and functions of the flash memory registers. 21.1 "Overview of Flash Memory" 21.2 "Flash Memory Registers" 21.3 "Flash Memory Operation" 21.4 "Automatic Algorithm of Flash Memory"...
Page 430: Overview Of Flash Memory
The flash memory in this device is a internal flash memory operating on 3 V. This flash memory is the same as the Fujitsu 2 megabit (512 Kb x 8 / 256 Kb x 16) flash memory MBM29LV400C except for a slight difference in the sector configuration. Writing to this flash memory from an external device with a ROM writer is also supported.
Page 431 CHAPTER 21 FLASH MEMORY I Block diagram of the flash memory Figure 21.1-1 "Block diagram of the flash memory" is a block diagram of the flash memory. Figure 21.1-1 Block diagram of the flash memory RDY/BUSYX Rising edge detection RESETX Control signal BYTEX generation...
Page 432 CHAPTER 21 FLASH MEMORY ❍ Memory map in CPU mode for MB91FV150 and MB91F155A Figure 21.1-3 "Memory map in CPU mode for MB91FV150 and MB91F155A" shows the memory map in CPU mode for MB91FV150 and MB91F155A. Figure 21.1-3 Memory map in CPU mode for MB91FV150 and MB91F155A I Sector address table Table 21.1-1 "Sector address table"...
Page 433 CHAPTER 21 FLASH MEMORY Table 21.1-1 Sector address table (Continued) Sector Corresponding bit Sector Address range address position capacity 0F4000,1 to 0F7FFC,D (16 bits from the LSB side) Bits 31 to 16 8 KB 0F8000,1 to 0FFFFC,D (16 bits from the LSB side) Bits 31 to 16 16 KB...
Page 434: Flash Memory Registers
CHAPTER 21 FLASH MEMORY 21.2 Flash Memory Registers Flash memory has a status register (FLCR) and a wait register (FWTC). I Status register (FLCR) (CPU mode) Register indicating the operating status of the flash memory. The FLCR controls CPU interrupts and writing to the flash memory.
Page 435 CHAPTER 21 FLASH MEMORY FLCR and the 16-bit free run timer share the interrupt sources shown in the table below. Interrupt No. Interrupt TBR default Interrupt source Offset In decimal In hexadecimal level address notation notation 16-bit free run timer/ ICR46 000FFF04 flash...
Page 436 CHAPTER 21 FLASH MEMORY [Bit 0]: LPM (Low power mode) Bit 0 is used to enable the function for decreasing power consumption other than through flash access during low-speed operation. Setting this bit to 1 prevents the flash memory circuit from being started when the address is changed.
Page 437: Flash Memory Operation
CHAPTER 21 FLASH MEMORY 21.3 Flash Memory Operation MB91130 provides the following two modes for accessing flash memory via the FR- CPU: • FR-CPU ROM mode In this mode, word data (32 bits) can be collectively read but cannot be written. •...
Page 438 CHAPTER 21 FLASH MEMORY CPU ROM mode. • When the RDY bit of the FLCR is 0, the value of the WE bit cannot be rewritten. Rewrite the value of the WE bit after verifying that the RDY bit is 1. ❍...
Page 439: Automatic Algorithm Of Flash Memory
CHAPTER 21 FLASH MEMORY 21.4 Automatic Algorithm of Flash Memory Commands for activating the automatic algorithms of the flash memory can be divided into four types: Read/Reset, Write, Chip Erase, and Sector Erase. The Sector Erase command is further divided into a Sector Erase Temporary Stop command and a Sector Erase Restart command.
Page 440 CHAPTER 21 FLASH MEMORY ❍ Read/Reset command The Read/Reset command sets the flash memory to read/reset mode. The flash memory maintains the read status until another command is entered. When the power supply is turned on, the flash memory is automatically set to read/reset mode. In this case, the Data Read command is unnecessary.
Page 441 CHAPTER 21 FLASH MEMORY the addresses of all sectors to be erased. The sector erase operation itself is performed in the time after writing the last Sector Erase command to when the 50µs timeout time has elapsed. Consequently, to erase several sectors at the same time, each of the sectors to be erased must be specified within 50µs.
Page 442 CHAPTER 21 FLASH MEMORY Bit 6 can read data from any address but bit 7 must read data from a write address. Note this when using the Sector Erase Temporary Stop command. To restart the sector erase operation, it is necessary to enter the Restart command (30 Further input of this Restart command at this point of time is ignored.
Page 443: Checking The Automatic Algorithm Execution Status
CHAPTER 21 FLASH MEMORY 21.5 Checking the Automatic Algorithm Execution Status The flash memory uses hardware for notifying the user of the internal operation status of flash memory and operation completion so as to perform the operation sequence for write/erase via the automatic algorithm. This automatic algorithm can use the following hardware sequence flags to check the operation status of flash memory: I Ready/Busy signal (RDY/BUSYX) Besides the hardware sequence flags, the flash memory has the Ready/Busy signal as a means...
Page 444 CHAPTER 21 FLASH MEMORY Table 21.5-1 Hardware sequence flag status Status DPOLL TOGLLE TLOVER SETIMR TOGGL2 Reverse Automatic write operation Toggle data Automatic erase operation Toggle Toggle Erase temporary stop read Toggle (Sector for which erase temporary stop is executed) Being Erase temporary executed...
Page 445 CHAPTER 21 FLASH MEMORY [Bit 7]: DPOLL (data polling flag) The data polling flag is used to notify the user with the data polling function that the automatic algorithm is being executed or has terminated. ❍ During write operation If read access is attempted when the automatic-write algorithm is being executed, flash memory outputs the inverse value of bit 7 in the last written data item, independently of the indicated address.
Page 446 CHAPTER 21 FLASH MEMORY [Bit 5]: TLOVER (timing limit excess flag) The timing limit excess flag notifies the user that automatic algorithm execution exceeded the time (internal pulse count) defined in the flash memory. ❍ At write/chip sector erase If the defined time (time required for write/erase) is not exceeded when read access is attempted after the automatic algorithm for write or chip sector erase has been activated, the timing limit excess flag becomes 0.
Page 447 CHAPTER 21 FLASH MEMORY ❍ At sector erase temporary stop If data is continuously read from the sector in the erase temporary stop status when flash memory is in erase temporary stop read mode, bit 2 performs toggle operation. If data is continuously read from a sector not in the erase temporary stop status when flash memory is in erase temporary stop write mode, Bit 2 outputs 1.
Page 448: Writing And Erasing Flash Memory
CHAPTER 21 FLASH MEMORY 21.6 Writing and Erasing Flash Memory This section describes how to issue the command that activates the automatic algorithm and how to perform read/reset, write, chip erase, sector erase, sector erase temporary stop, and sector erase restart operations for the flash memory. I Overview of writing and erasing flash memory Executing the write cycle for each command sequence bus during read/reset, write, chip erase, sector erase, sector erase temporary stop, or erase restart operation enables the flash memory...
Page 449: Putting Flash Memory Into Read/Reset Status
CHAPTER 21 FLASH MEMORY 21.6.1 Putting flash memory into read/reset status This section describes how to place the flash memory in the read/reset status by issuing the Read/Reset command. I Placing the flash memory in read/reset status The flash memory can be placed in the read/reset status by continuously transmitting the Read/ Reset command form the command sequence table to sectors in the flash memory.
Page 450: Writing Data To Flash Memory
CHAPTER 21 FLASH MEMORY 21.6.2 Writing data to flash memory This section describes how to write data to the flash memory by issuing the Write command. I Writing data to the flash memory The automatic algorithm for writing flash memory data can be activated by continuously issuing the Write command (see Table 21.4-1 "Command sequence") to target sectors in the flash memory.
Page 451 CHAPTER 21 FLASH MEMORY Figure 21.6-1 Example of flash memory write procedure Start of write FLCR: WE(bit5) Enable flash memory write Write command sequence D5555 CAAAB D5555 Write address write data Read internal address Next address Data Is data polling (DPOLL) Data or not Data? Data...
Page 452: Erasing Data
CHAPTER 21 FLASH MEMORY 21.6.3 Erasing data There are two methods for erasing data in this device. One is chip erase and the other is sector erase. Chip erase is used to erase the data of the whole chip and sector erase is used to erase data in units of sectors.
Page 453 CHAPTER 21 FLASH MEMORY The data polling flag (DPOLL) changes simultaneously with changes in the timing limit excess flag (TLOVER). For this reason, the data polling flag bit (DPOLL) must be rechecked. Figure 21.6-2 Example of the procedure for flash memory sector erase Start of erase FLCR: WE(bit5) Enable flash memory erase...
Page 454: Temporarily Stopping And Restarting Sector Erase
CHAPTER 21 FLASH MEMORY 21.6.4 Temporarily Stopping and Restarting Sector Erase This section describes how to temporarily stop flash memory sector erase by issuing the Sector Erase Temporary Stop command and how to restart the temporarily stopped flash memory sector erase by issuing the Sector Erase Restart command. During this operation, data can still be read from sectors not erased.
Page 455: Appendix
APPENDIX These appendixes provide the I/O map, notes on using the little-endian area, and instruction lists. They also explain interrupt vectors and the pin status in each CPU state. APPENDIX A "I/O Map" APPENDIX B "Interrupt Vectors" APPENDIX C "Pin Status in Each CPU State" APPENDIX D "Notes on Using the Little-Endian Area"...
Page 456: Appendix A I/O Map
APPENDIX APPENDIX A I/O Map Figure A-1 "How to use the I/O" shows how to use the I/O map, and Table A-1 "I/O map" shows the I/O map itself (which indicates the correspondence between the memory area and peripheral resources for each register). I How to use the I/O map How to use the I/O Figure A-1...
Page 457 APPENDIX A I/O Map I I/O map Table A-1 I/O map Register Address Block PDR3 [R/W] PDR2 [R/W] 000000 XXXXXXXX XXXXXXXX PDR6 [R/W] PDR5 [R/W] PDR4 [R/W] 000004 XXXXXXXX XXXXXXXX XXXXXXXX PDR8 [R/W] 000008 -XXXXXXX Port data 00000C register PDRF [R/W] PDRE [R/W] PDRD [R/W] PDRC [R/W]...
Page 458 APPENDIX Table A-1 I/O map (Continued) Register Address Block TMRLR3 TMR3 000044 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload timer 3 TMCSR3 [R/W] 000048 ----0000 00000000 CDCR1 [R/W] CDCR0 [R/W] 00004C 0---0000 0---0000 Communication prescaler 1 CDCR3 [R/W] CDCR2 [R/W] 000050 0---0000 0---0000 000054 Reserved...
Page 459 APPENDIX A I/O Map Table A-1 I/O map (Continued) Register Address Block GCN1 [R/W] GCN2 [R/W] 000094 PPG control 00110010 00010000 00000000 PTMR0 PCSR0 000098 11111111 11111111 XXXXXXXX XXXXXXXX PPG0 PDUT0 PCNH0 [R/W, W] PCNL0 [R/W] 00009C XXXXXXXX XXXXXXXX 0000000- 00000000 PTMR1 PCSR1...
Page 460 APPENDIX Table A-1 I/O map (Continued) Register Address Block AICK [R/W] Analog input 0000E8 00000000 control 0000EC Reserved 000 F0 PCRH [R/W] PCRI [R/W] PCRD [R/W] PCRC [R/W] Pull-up control 0000F4 --000000 --000000 00000000 00000000 OCRH [R/W] OCRI [R/W] Open-drain 0000F8 --000000 --000000...
Page 461 APPENDIX A I/O Map Table A-1 I/O map (Continued) Register Address Block 000220 Reserved 0003EC BSD0 0003F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] 0003F4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit search module BSDC 0003F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR 0003FC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICR00 [R/W] ICR01 [R/W] ICR02 [R/W]...
Page 462 APPENDIX Table A-1 I/O map (Continued) Register Address Block 000434 Reserved 00047C RSRR/WTCR [R, W] STCR [R/W, W] PDRR [R/W] CTBR [W] 000480 1-XXX-00 000111-- ----0000 XXXXXXXX Clock control unit GCR [R/W, R] WPR [W] 000484 110011-1 XXXXXXXX PCTR [R/W] 000488 PLL control 00XX0XXX...
Page 463 APPENDIX A I/O Map Table A-1 I/O map (Continued) Register Address Block 000634 Reserved 0007BC FLCR [R/W, R] 0007C0 000XXXX0 FLASH control FWTC [R/W, W] 0007C4 -----000 0007C8 Reserved 0007F8 Little Endian MODR [W] 0007FC register -----000 XXXXXXXX Mode register Notes: Do not execute a read-modify-write (RMW) instruction for a register with a Write-Only bit.
Page 464: Appendix B Interrupt Vectors
APPENDIX APPENDIX B Interrupt Vectors Table B-1 "Interrupt vectors" is the interrupt vector table. This table lists the MB91150 interrupt sources and assignment of interrupt vectors to interrupt control registers. I Interrupt vectors • ICR: Register located in the interrupt controller. This register sets an interrupt level for each interrupt request.
Page 465 APPENDIX B Interrupt Vectors Table B-1 Interrupt vectors (Continued) Interrupt number Interrupt TBR default Interrupt source Offset Decimal Hexadeci level address notation Undefined instruction exception 000FFFC4 System-reserved 000FFFC0 External interrupt 0 ICR00 000FFFBC External interrupt 1 ICR01 000FFFB8 External interrupt 2 ICR02 000FFFB4 External interrupt 3...
Page 466 APPENDIX Table B-1 Interrupt vectors (Continued) Interrupt number Interrupt TBR default Interrupt source Offset Decimal Hexadeci level address notation PPG1 ICR28 000FFF4C PPG2 ICR29 000FFF48 PPG3 ICR30 000FFF44 PPG4 ICR31 000FFF40 PPG5 ICR32 000FFF3C U/D counter 0 (compare/underflow, ICR33 000FFF38 overflow, up/down inversion) U/D counter 1 (compare/underflow, ICR34...
Page 467 APPENDIX B Interrupt Vectors Table B-1 Interrupt vectors (Continued) Interrupt number Interrupt TBR default Interrupt source Offset Decimal Hexadeci level address notation System-reserved 000FFEDC System-reserved 000FFED8 System-reserved 000FFED4 System-reserved 000FFED0 System-reserved 000FFECC System-reserved 000FFEC8 System-reserved 000FFEC4 System-reserved 000FFEC0 00FFEBC Used by INT instruction 00FFC00 REALOS/FR uses 0x40 and 0x41 interrupts for system codes.
Page 468: Appendix C Pin Status In Each Cpu State
APPENDIX APPENDIX C Pin Status in Each CPU State Table C-1 "Terms related to pin status" explains the terms related to pin status, and Table C-2 "Pin status in 16-bit mode of the external bus" to Table C-4 "Pin status in single-chip mode"...
Page 469 APPENDIX C Pin Status in Each CPU State I Pin status in each CPU state Table C-2 Pin status in 16-bit mode of the external bus In stop mode Bus release At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (BGRNT=1) (RST=1)
Page 470 APPENDIX Table C-2 Pin status in 16-bit mode of the external bus (Continued) In stop mode Bus release At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (BGRNT=1) (RST=1) PE0-7 OC0-7 Last status Last status Output Hi-Z or Last status Output Hi-Z or retained retained or keep...
Page 471 APPENDIX C Pin Status in Each CPU State Table C-3 Pin status in external bus 8-bit mode In stop mode Bus release At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (BGRNT=1) (RST=1) Last status Last status Output Hi-Z or Last status P20-7 Port Output Hi-Z or...
Page 472 APPENDIX Table C-3 Pin status in external bus 8-bit mode (Continued) In stop mode Bus release At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (BGRNT=1) (RST=1) PE0-7 OC0-7 Last status Last status Output Hi-Z or Last status Output Hi-Z or retained retained or keep keep the input at...
Page 473 APPENDIX C Pin Status in Each CPU State Table C-4 Pin status in single-chip mode In stop mode At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (RST=1) P20-7 Port Last status Last status Output Hi-Z or Output Hi-Z or retained retained or keep keep the input at...
Page 474 APPENDIX Table C-4 Pin status in single-chip mode (Continued) In stop mode At reset Function In sleep mode Remarks name HIZX=0 HIZX=1 (RST=1) SOT1 Last status Last status Output Hi-Z or Output Hi-Z or retained retained or keep keep the input at enable all-pin SCK1/TO1 the input at 0...
Page 475: Appendix D Notes On Using The Little-Endian Area
APPENDIX D Notes on Using the Little-Endian Area APPENDIX D Notes on Using the Little-Endian Area This appendix provides notes on using the little-endian area for each of the following items: D.1 "C Compiler (fcc911)" D.2 "Assembler (fasm911)" D.3 "Linker (flnk911)" D.4 "Debuggers (sim911, eml911, and mon911)"...
Page 476: C Compiler (Fcc911)
APPENDIX C Compiler (fcc911) When programming in C, note that the operation result is unpredictable if the following operations are performed for the little-endian area: • Allocation of variables having initial values • Structure insertion • Manipulation of a non-character type array by using a character-string handling function •...
Page 477 APPENDIX D Notes on Using the Little-Endian Area If structure member locations do not match, do not allocate structure variables in the little- endian area. I Manipulation of a non-character type array by using a character-string handling function The character-string handling functions provided in the standard library perform processing in units of bytes.
Page 478 APPENDIX I Using double type and long-double type During access to data of double or long-double type, a word in either the higher bits or the lower bits of the data is accessed. Access to double type and long-double type variables allocated in the little-endian area does therefore not produce correct results.
Page 479: Assembler (Fasm911)
APPENDIX D Notes on Using the Little-Endian Area Assembler (fasm911) When programming in the assembler language for the FR Series, note the following for the little-endian area with respect to the items below: • Sections • Data access I Sections The little-endian area is used mainly for data exchange with CPUs employing the little-endian system.
Page 480: Linker (Flnk911)
APPENDIX Linker (flnk911) This section provides notes related to the following topics for the section placement at linkage when a program that uses the little-endian area is to be created: • Restrictions on section types • Failure to detect errors I Restriction on section types Only data sections without initial values can be allocated in the little-endian area.
Page 481: Debuggers (Sim911, Eml911, And Mon911)
APPENDIX D Notes on Using the Little-Endian Area Debuggers (sim911, eml911, and mon911) This section provides notes on using the simulator debugger, emulator debugger, and monitor debugger. I Simulator debugger There is no memory space specification command that explicitly indicates the little-endian area. Therefore, memory operation commands and memory operation instructions are handled in big- endian mode.
Page 482: Appendix E Instruction Lists
APPENDIX APPENDIX E Instruction Lists This appendix lists the FR Series instructions. For facilitating understanding the instruction list, notes on the following items are provided: • How to read the instruction lists • Addressing mode symbols • Instruction format I How to read the instruction lists Mnemonic Type CYCLE...
Page 483 APPENDIX E Instruction Lists 7) Indicates the operation of the instruction. I Addressing mode symbols Table E-1 Explanations of the addressing mode symbols Symbol Meaning Register direct (R0 to R15, AC, FP, and SP) Register direct (R0 to R15, AC, FP, and SP) Register direct (R13 and AC) Register direct (program status register) Register direct (TBR, RP, SSP, USP, MDH, and MDL)
Page 484 APPENDIX Table E-1 Explanations of the addressing mode symbols (Continued) Symbol Meaning @(R14,disp9) Register relative indirect (disp9: -0x100 to 0xFE, only multiples of 2) @(R14,disp8) Register relative indirect (disp8: -0x80 to 0x7F) @(R15,udisp6) Register relative indirect (udisp6: 0 to 60, only multiples of 4) @Ri+ Register indirect with post-increment (R0 to R15, AC, FP, and SP) @R13+...
Page 485 APPENDIX E Instruction Lists I Instruction format Table E-2 Instruction format Type Instruction format 16 bit i8/o8 u4/m4 C’ Only for ADD, ADDN, CMP, LSL, LSR, and ASR instructions s5/u5 u8/re18/dir/ reglist SUB-OP re111...
Page 486 APPENDIX I FR Series instruction lists This section provides lists of the FR Series instructions in the following order: • Table E-3 "Addition and subtraction instructions" • Table E-4 "Comparison operation instructions" • Table E-5 "Logical operation instructions" • Table E-6 "Bit manipulation instructions" •...
Page 487 APPENDIX E Instruction Lists I Addition and subtraction instructions Table E-3 Addition and subtraction instructions Mnemonic Type CYCLE NZVC Operation Remarks ADD Rj, Ri CCCC Ri+Rj --> Ri *ADD #s5, Ri C’ CCCC Ri+s5 --> Ri The assembler assumes the higher one bit to be a symbol.
Page 488 APPENDIX I Logical operation instructions Table E-5 Logical operation instructions Mnemonic Type CYCLE NZVC Operation Remarks AND Rj, Ri CC-- Ri &= Rj Word AND Rj, @Ri 1+2a CC-- (Ri) &= Rj Word ANDH Rj, @Ri 1+2a CC-- (Ri) &= Rj Half word ANDB Rj, @Ri 1+2a...
Page 489 APPENDIX E Instruction Lists I Bit manipulation instructions Table E-6 Bit manipulation instructions Mnemonic Type CYCLE NZVC Operation Remarks BANDL #u4, @Ri 1+2a ---- (Ri) &=(0xF0+u4) Manipulation of the lower four bits BANDH #u4, @Ri 1+2a ---- (Ri) &=((u4<<4)+0x0F) Manipulation of the higher four bits *BAND #u8, @Ri ----...
Page 490 APPENDIX I Multiplication and division instructions Table E-7 Multiplication and division instructions Mnemonic Type CYCLE NZVC Operation Remarks MUL Rj,Ri CCC- Ri * Rj --> MDH,MDL 32bit*32bit=64bit MULU Rj,Ri CCC- Ri * Rj --> MDH,MDL Unsigned MULH Rj,Ri CC-- Ri * Rj --> MDL 16bit*16bit=32bit MULUH Rj,Ri CC--...
Page 491 APPENDIX E Instruction Lists I Shift instructions Table E-8 Shift instructions Mnemonic Type CYCLE NZVC Operation Remarks LSL Rj, Ri CC-C Ri << Rj --> Ri Logical shift *LSL # u5, Ri (u5:0 to 31) C’ CC-C Ri << u5 --> Ri LSL #u4, Ri CC-C Ri <<...
Page 492 APPENDIX I Memory load instructions Table E-10 Memory load instructions Mnemonic Type CYCLE NZVC Operation Remarks LD @Rj, Ri ---- (Rj) --> Ri LD @(R13,Rj), Ri ---- (R13+Rj) --> Ri LD @(R14,disp10), Ri ---- (R14+disp10) --> Ri LD @(R15,udisp6), Ri ---- (R15+udisp6) -->...
Page 493 APPENDIX E Instruction Lists I Memory store instructions Table E-11 Memory store instructions Mnemonic Type CYCLE NZVC Operation Remarks ST Ri, @ Rj ---- Ri --> (Rj) Word ST Ri, @ (R13,Rj) ---- Ri --> (R13+Rj) Word ST Ri, @ (R14,disp10) ---- Ri -->...
Page 494 APPENDIX I Ordinary branch (no delay) instructions Table E-13 Ordinary branch (no delay) instructions Mnemonic Type CYCLE NZVC Operation Remarks JMP @Ri 97-0 ---- Rj --> PC CALL label12 ---- PC+2 --> RP, PC+2+(label12-PC-2) --> PC CALL @Ri 97-1 ---- PC+2 -->...
Page 495 APPENDIX E Instruction Lists I Delayed branch instructions Table E-14 Delayed branch instructions Mnemonic Type CYCLE NZVC Operation Remarks JMP:D @Ri 9F-0 ---- Ri --> PC CALL:D label12 ---- PC+4 --> RP , PC+2+(label12-PC-2) --> PC CALL:D @Ri 9F-1 ---- PC+4 -->...
Page 496 APPENDIX I Other instructions Table E-15 Other instructions Mnemonic Type CYCLE NZVC Operation Remarks 9F-A ---- No change ANDCCR #u8 CCCC CCR and u8 --> CCR ORCCR #u8 CCCC CCR or u8 --> CCR STILM #u8 ---- i8 --> ILM ILM immediate value set ADDSP #s10...
Page 497 APPENDIX E Instruction Lists I 20-bit ordinary branch macroinstructions Table E-16 20-bit ordinary branch macroinstructions Mnemonic Operation Remarks *CALL20 label20,Ri Address of the next instruction --> RP Ri: Temporary register (See Reference 1.) label20 --> PC *BRA20 label20,Ri label20 --> PC Ri: Temporary register (See Reference 2.) *BEQ20 label20,Ri if(Z==1) then label20 -->PC...
Page 498 APPENDIX I 20-bit delayed branch macroinstructions Table E-17 20-bit delayed branch macroinstructions Mnemonic Operation Remarks *CALL20:D label20,Ri Address of the next instruction + 2 Ri: Temporary register (See Reference 1.) --> RP label20 --> PC *BRA20:D label20,Ri label20 --> PC Ri: Temporary register (See Reference 2.) *BEQ20:D label20,Ri if(Z==1) then label20 -->PC...
Page 499 APPENDIX E Instruction Lists I 32-bit ordinary branch macroinstructions Table E-18 32-bit ordinary branch macroinstructions Mnemonic Operation Remarks *CALL32 label32,Ri Address of the next instruction --> RP Ri: Temporary register (See Reference 1.) label32 --> PC *BRA32 label32,Ri label32 --> PC Ri: Temporary register (See Reference 2.) *BEQ32 label32,Ri if(Z==1) then label32 -->PC...
Page 500 APPENDIX I 32-bit delayed branch macroinstructions Table E-19 32-bit delayed branch macroinstructions .Mnemonic Operation Remarks *CALL32:D label32,Ri Address of the next instruction + 2 Ri: Temporary register (See Reference 1.) --> RP label32 --> PC *BRA32:D label32,Ri label32 --> PC Ri: Temporary register (See Reference 2.) *BEQ32:D label32,Ri if(Z==1) then label32 -->PC...
Page 501 APPENDIX E Instruction Lists I Direct addressing instructions Table E-20 Direct addressing instructions Mnemonic Type CYCLE NZVC Operation Remarks DMOV @dir10, R13 ---- (dir10) --> R13 Word DMOV R13, @dir10 ---- R13 --> (dir10) Word DMOV @dir10, @R13+ ---- (dir10) --> (R13),R13+=4 Word DMOV @R13+, @dir10 ----...
Page 502 APPENDIX I Coprocessor control instructions Table E-22 Coprocessor control instructions Mnemonic Type CYCLE NZVC Operation Remarks COPOP #u4, #u8, CRj, CRi 9F-C ---- Arithmetic operation indication COPLD #u4, #u8, Rj, CRi 9F-D 1+2a ---- Rj --> CRi COPST #u4, #u8, CRj, Ri 9F-E 1+2a ----...
Page 503: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 504 INDEX Index Numerics 0 detection............397 A/D control status register 0 (ADCS0) ....285 0 detection data register (BSD0) ......395 A/D converted data preservation function.... 292 1 detection............397 A/D data register (ADCR) ........287 1 detection data register (BSD1) ......395 access in little-endian and big-endian mode, difference and similarity ......
Page 505 INDEX branch instruction with delay slot, restriction on ..51 continuous transfer mode ........374 continuous-conversion mode, operation in...290 branch instruction without delay slot ...... 52 branch instruction without delay slot, explanation of control register............271 ..............52 control register (SCR0-3)........312 burst transfer............378 control status register (PCNH, PCNL) ....205 burst transfer mode..........
Page 506 INDEX descriptor start word..........370 external level register (ELVR) ......252 external pin control register 0....... 110 descriptor, second word in ........372 descriptor, third word in........372 external pin control register 1....... 112 detect error, failure to ........... 464 external reset input ..........
Page 507 INDEX I/O map, how to use..........440 little-endian register ..........113 logical operation instruction ........472 I/O port block diagram.......... 150 I/O port register ............ 150 low-power consumption mode operation....88 I/O port with a pull-up resistor, block diagram of.. 152 low-power consumption mode, status transition of.95 I/O port with open-drain output function and pull-up resistor, block diagram of......
Page 508 INDEX operation of branch instruction with delay slot, reload and compare function are enabled explanation of..........49 simultaneously, when ........ 182 ordinary branch (no delay) instruction ....478 reload and compare function, example for selection of ..............181 other instruction............ 480 reload function is enabled, when ......
Page 509 INDEX stop control block, block diagram of....... 89 UART baud-rate selection circuit......327 UART block diagram ..........306 stop control register 0 (STPR0) ......401 stop control register 1 (STPR1) ......402 UART function ............304 stop control register 2 (STPR2) ......403 UART interrupt............322 stop state, return from..........
Page 510 INDEX...
Page 511 CM71-10110-4E FUJITSU SEMICONDUCTOR FR30 32-BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL April 2003 the fourth edition FUJITSU LIMITED Electronic Devices Published Edited Business Promotion Dept.

Fujitsu MB91150 Series Hardware Manual

Chapter 1 Overview of the Mb91150

Chapter 2 Handling the Device

Chapter 3 Memory Space, Cpu and Control Unit

Chapter 4 Bus Interface

Chapter 5 I/O Ports

Chapter 6 8/16-Bit Up/Down Counter/Timer

Chapter 7 16-Bit Reload Timer

Chapter 8 Ppg Timer

Chapter 9 Multifunctional Timer

Chapter 10 External Interrupt Control Block

Chapter 11 Delayed Interrupt Module

Chapter 12 Interrupt Controller

Chapter 13 8/10-Bit A/D Converter

Chapter 14 8-Bit D/A Converter

Chapter 15 Uart

Chapter 16 I 2 C Interface

Chapter 17 Dma Controller

Chapter 18 Bit-Search Module

Chapter 19 Peripheral Stop Control

Chapter 20 Calendar Macros

Chapter 21 Flash Memory

Appendix

APPENDIX A I/O Map

APPENDIX B Interrupt Vectors

APPENDIX C Pin Status in each CPU State

APPENDIX D Notes on Using the Little-Endian Area

APPENDIX E Instruction Lists

Index

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Summary of Contents for Fujitsu MB91150 Series