Fujitsu MB96300 series Hardware Manual page 492

CHAPTER 20 USART
Table 20.4-3 Functions of each bit of status register (SSRn)
Bit name
bit14 ORE:
Overrun error flag bit
bit13 FRE:
Framing error flag bit
bit12 RDRF:
Receive data full flag
bit
bit11 TDRE:
Transmission data
empty flag bit
bit10 BDS:
Transfer direction
selection bit
bit9 RIE:
receive interrupt
request enable bit
bit8 TIE:
Transmission
interrupt request
enable bit
484
• This bit is set to 1 when an overrun error occurs during reception.
• It is cleared when 1 is written to the CRE bit of the serial control register (SCRn).
• In Mode 3, it is also cleared when ESCRn:LBD = 1.
• A receive interrupt request is output when this bit and the RIE bit are 1.
• Data in the reception data register (RDRn) is invalid when this flag is set.
• This bit is set to 1 when a framing error occurs during reception.
• It is cleared when 1 is written to the CRE bit of the serial control register 1 (SCRn).
• In Mode 3, it is also cleared when ESCRn:LBD = 1.
• A receive interrupt request is output when this bit and the RIE bit are 1.
• Data in the reception data register (RDRn) is invalid when this flag is set.
• This flag indicates the status of the reception data register (RDRn).
• This bit is set to 1 when reception data is loaded into RDRn
• It is cleared when the reception data register (RDRn) is read.
• In Mode 3, it is also cleared when ESCRn:LBD = 1.
• A receive interrupt request is output when this bit and the RIE bit are 1.
Note:
ESIR:RDRF has the same behaviour as this bit, but it is not cleared when the
reception data register (RDRn) is read.
• This flag indicates the status of the transmission data register (TDRn).
• This bit is cleared to 0 when transmission data is written to TDRn and is set to 1
when data is loaded into the transmission shift register and transmission starts.
• A transmission interrupt request is generated if both this bit and the TIE bit are 1.
• If the LBR bit in the ECCRn register is set to "1" while the TDRE bit is "1", then this
bit once changes to "0". After the completion of LIN synch break generator, the
TDRE bit charges back to "1".
Note:
This bit is set to 1 (TDRn empty) as its initial value.
Note:
ESIR:TDRE has the same behaviour as this bit, but it is not cleared when
transmission data is written to TDRn.
• This bit selects whether to transfer serial data from the least significant bit (LSB first,
BDS=0) or the most significant bit (MSB first, BDS=1).
Note:
The high-order and low-order sides of serial data are interchanged with each other
during reading from or writing to the serial data register. If this bit is set to another
value after the data is written to the RDRn register, the data becomes invalid.
• This bit is fixed to 0 in mode 3 (LIN)
• This bit enables/disables the receive interrupt. If any of the RDRF, PE, ORE and
FRE bits is set and this bit is "1", then a receive interrupt is signaled to the interrupt
controller.
• This bit enables or disables the transmission interrupt.
• A transmission interrupt request is output when this bit and the TDRE bit are 1.
MB96300 Super Series Hardware Manual
Function