Fujitsu MB96300 series Hardware Manual page 478

CHAPTER 20 USART
Peripheral clock
AICD
RBI
RDRF
ESIRn
TDRE
register
●
Reload Counter
The reload counter functions as the dedicated baud rate generator. It can select external input clock or
internal clock for the transmitting and receiving clocks. The reload counter has a 16-bit register for the reload
value. The actual count of the transmission reload counter can be read via the BGRn.
●
Reception Control Circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity
counter. The received bit counter counts reception data bits. When reception of one data item for the
specified data length is complete, the received bit counter sets the reception data register full flag. The start
470
Figure 20.2-1 Block diagram of USART
(OTO,
EXT,
REST)
transmission clock
Reload
reception clock
Counter
SCKn
RECEPTION
CONTROL
CIRCUIT
Pin
Restart Reception
Reload Counter
SINn
Pin
Over-
sampling
Unit
LIN break
Signal
and Synch
to ICU
Field
Detection
circuit
Error
Detection
PE
DMA STOP ORE
FRE
PE
MD1
ORE
MD0
FRE
OTO
SMRn
SSRn
RDRF EXT
register register
REST
TDRE
BDS UPCL
RIE SCKE
TIE SOE
MB96300 Super Series Hardware Manual
TRANSMISSION
CONTROL
CIRCUIT
Start bit
Transmission
Detection
Start circuit
circuit
Received Transmission
Bit counter Bit counter
Received
Transmission
Parity counter
Parity counter
RDRF
reception
complete
SINx
Reception
Transmission
shift register shift register
RDRn
TDRn
LBD
Internal data bus
LBIE
PEN
P LBD
SBL
LBL1
ESCRn
SCRn
CL LBL0
register
register
A/D SOPE
CRE
SIOP
RXE CCO
TXE SCES
n = 0...9 according to device ( Please refer to
the datasheet of the corresponding device)
AICD
PE ORE FRE
TIE
RIE
LBIE
Interrupt
LBD
Generation
BIE
circuit
RBI
TBI
reception
IRQ
transm.
TDRE
IRQ
SOTn
Pin
SOTx
SINx
LIN
break
genera-
tion
transmission
circuit
start
Bus idle
Detection
LBR
circuit
LBL1
LBL0
RBI TBI
LBR
MS
ECCRn
SCDE
register
SSM
BIE
RBI
TBI