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MB96300 Super Series Hardware Manual
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Receive interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status
Register (SSRn) and the Extended Serial Interrupt Register (ESIRn) is set to "1":
• Data reception is complete, i. e. the received data was transferred from the serial input shift register to the
Reception Data Register (RDRn) and data can be read: SSRn:RDRF, ESIRn:RDRF
• Overrun error, i. e. SSRn:RDRF = 1 and RDR was not read by the CPU and received next serial data:
SSRn:ORE
• Framing error, i. e. a stop bit was expected, but a "0"-bit was received: SSRn:FRE
• Parity error, i. e. a wrong parity bit was detected: SSRn:PE
If ESIR:AICD = 0 and at least one of the flag bits SSRn:RDRF, SSRn:ORE, SSRn:FRE, SSRn: PE is set to
"1" and the receive interrupt is enabled (SSRn:RIE = 1), a receive interrupt request is generated.
If ESIR:AICD = 1 and at least one of the flag bits ESIRn:RDRF, SSRn:ORE, SSRn:FRE, SSRn: PE is set to
"1" and the receive interrupt is enabled (SSRn:RIE = 1), a receive interrupt request is generated.
If the Reception Data Register (RDRn) is read, the SSRn:RDRF flag is automatically cleared to "0". Note
that this is the only way to reset the SSRn:RDRF flag.
The error flags are cleared to "0", if a "1" is written to the Clear Reception Error (CRE) flag bit of the Serial
Control Register (SCRn). The RDRn contains only valid data if the RDRF flag is "1" and no error bits are
set.
Note that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one CLKP1
clock cycle.
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Transmission Interrupt
If transmission data is transferred from the Transmission Data Register (TDRn) to the transfer shift register
and transfer is started, the Transmission Data Register Empty flag bit (TDRE) of the Serial Status Register
(SSR) is set to "1". In this case an interrupt request is generated, if the Transmission Interrupt Enable (TIE)
bit of the SSR was set to "1" before.
Note, that the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing
data to the Transmission Data Register (TDRn).
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Bus Idle Interrupt
If no reception is ongoing at the SINn pin, the bits ECCRn:RBI and ESIRn:RBI are set to "1". ECCRn:RBI is
cleared as soon as reception is starting, while ESIRn:RBI must be cleared explicitely by writing "0" to this
bit.
If no transmission is ongoing at the SOTn pin, the bit ECCRn:TBI is set to "1". When transmission is
starting, ECCRn:TBI is cleared again.
If ESIRn:AICD = "0" and ECCRn:BIE = "1", the interrupt is generated as soon as both ECCRn:RBI and
ECCRn:TBI are "1". It is cleared as soon as either ECCRn:RBI or ECCRn:TBI is cleared. Do not use the bus
idle interrupt with AICD = "0", because ECCRn:RBI may be cleared before the interrupt handling software is
able to clear the interrupt.
If ESIRn:AICD = "1" and ECCRn:BIE = "1", the interrupt is generated as soon as both ESIRn:RBI and
ECCRn:TBI are "1". It is cleared as soon as either ESIRn:RBI or ECCRn:TBI is cleared. Use the bus idle
interrupt with ESIRn:AICD = 1, because both ESIRn:RBI and ECCRn:TBI are acknowlegde by the interrupt
CHAPTER 20 USART
497
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