Fujitsu MB96300 series Hardware Manual page 125

MB96300 Super Series Hardware Manual
• Automatic data transfer between peripheral resources (I/O) and memory
• CPU bus allocation during DMA transfer
• Up to 16 DMA transfer channels with fixed priority scheme (the smaller the DMA channel number, the
higher the priority of the request).
• Allow selection of whether or not to increment the transfer source and destination addresses (the buffer
address may either be incremented or left unchanged; the I/O register address may either be incremented
or left unchanged).
• DMA transfer can be started by a selectable peripheral resource interrupt (hardware IRQ).
• The DMA transfer is controlled by:
- The DMA Enable Register (DER, bits 0...15)
- The DMA interrupt select registers (DISEL 0 ... 15)
- The DMA Stop Status Register (DSSR, bits 0...15)
- The DMA Status Register (DSR, bits 0...15)
- The DMA descriptors (8 byte each; DCT, IOA, DMACS, BAP)
• DMA transfer can be stopped upon an error condition in the peripheral resource.
• At the end of a DMA transfer, processing automatically branches to the according interrupt service routine
of the peripheral resource.
■ Structure
If enabled, the DMA controller serves interrupt requests of peripheral resources before they are passed to the
interrupt controller. The structure of the interrupt system can be understood in that way, that the DMA
controller is placed between the peripheral resources (IRQ sources) and the interrupt controller (see Figure
3.6-1 "Occurrence and release of hardware interrupt").
I/O service by DMA is handled by following units:
• Peripheral resources
- IF, IE: Interrupt flag and enable bits are used to control interrupt requests from resources (IRQ = IF
&& IE).
• DMA controller
- DER and DISEL enable the DMA operation for a selected interrupt request. If DMA operation is not
enabled, the request is passed to the interrupt controller.
- Transfer information is stored in the DMA descriptors (data count, I/O address pointer, Buffer Address
Pointer and control information).
- The DMA controller processes the request (data transfer from/to peripheral) and clears the interrupt
flag in the peripheral resource.
- The DMA controller identifies its status (DSR) and indicates, if a stop condition has occured (DSSR).
In case of DMA is stopped or completed, an interrupt is issued to the interrupt controller.
• Interrupt controller
- The interrupt controller handles the interrupt due to completion or cancellation of DMA.
- The ICR assigns interrupt levels, which determine the priority levels of simultaneously requested
interrupts.
• CPU
CHAPTER 4 DMA
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