Fujitsu MB96300 series Hardware Manual page 927

MB96300 Super Series Hardware Manual
Table A-1 I/O map of MB96V300 (9/50)
Address
0000E3H USART3 - Ext. Status Register
0000E4H USART3 - Baud Rate Generator Register Low
0000E5H USART3 - Baud Rate Generator Register High
0000E6H USART3 - Extended Serial Interrupt Register
0000F0H External bus
000100H DMA0 - Buffer address pointer low byte
000101H DMA0 - Buffer address pointer middle byte
000102H DMA0 - Buffer address pointer high byte
000103H DMA0 - DMA control register
000104H DMA0 - I/O register address pointer low byte
000105H DMA0 - I/O register address pointer high byte
000106H DMA0 - Data counter low byte
000107H DMA0 - Data counter high byte
000108H DMA1 - Buffer address pointer low byte
000109H DMA1 - Buffer address pointer middle byte
00010AH DMA1 - Buffer address pointer high byte
00010BH DMA1 - DMA control register
00010CH DMA1 - I/O register address pointer low byte
00010DH DMA1 - I/O register address pointer high byte
00010EH DMA1 - Data counter low byte
00010FH DMA1 - Data counter high byte
000110H DMA2 - Buffer address pointer low byte
000111H DMA2 - Buffer address pointer middle byte
000112H DMA2 - Buffer address pointer high byte
000113H DMA2 - DMA control register
000114H DMA2 - I/O register address pointer low byte
000115H DMA2 - I/O register address pointer high byte
000116H DMA2 - Data counter low byte
000117H DMA2 - Data counter high byte
000118H DMA3 - Buffer address pointer low byte
Register
APPENDIX A I/O Map of MB96V300
Abbreviation Abbreviation
8-bit access 16-bit access
ESCR3
BGRL3 BGR3
BGRH3
ESIR3
EXTBUS0
BAPL0
BAPM0
BAPH0
DMACS0
IOAL0 IOA0
IOAH0
DCTL0 DCT0
DCTH0
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1 IOA1
IOAH1
DCTL1 DCT1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2 IOA2
IOAH2
DCTL2 DCT2
DCTH2
BAPL3
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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