Cautions - Fujitsu MB96300 series Hardware Manual

CHAPTER 24 REAL TIME CLOCK
24.4

Cautions

This section describes the cautions to be considered while using the Real Time Clock
■ Cautions
• Setting the interrupt request flags (WTCR:INT0, WTCR:INT1, WTCR:INT2, WTCR:INT4 and
WTCER:INT4) to "1" due to overflow, and writing "0" to that bit have occurred at the same time, the flag
is set to "1" (Flag setting takes precedence).
• Writing "1" to the update bit (WTCR:UPDT) and update completion have occurred at the same time, the
update bit (UPDT) is set to "0".
• When the second counter holds the value of 59, even if "1" is written to the update bit (WTCR:UPDT),
the hour/minute/second counters are not updated, leaving the update bit to remain "0".
In order to update the hour/minute/second counters, it is recommended that "0" should be written to the
start bit (WTCR:ST), the hour/minute/second counters be cleared to "0", and then "1" be written to the
start bit (ST).
• If you stop the peripheral clock (CLKP1) after updating the hour/minute/second counters using the update
bit (WTCR:UPDT), read the hour/minute/second registers to confirm that they have been updated before
stopping the peripheral clock CLKP1.
• When you start to use the Real Time Clock module, change the start bit (ST) from "1" to "0", and clear
the hour/minute/second counters and the 21 bit down counter to "0".
• The Sub-second register of the RTC module stores the reload value for the 21bit prescaler. This value is
reloaded after the reload counter reaches "0". When modifying all three bytes, make sure the reload
operation will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the
incorrect value of the combination of new data and old data bytes. It is generally recommended that the
Sub-Second register is updated while the ST bit is "0".
• However, if this update is done immediately after an RTC second interrupt there should be enough time to
securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to
"0" and the module is in operation.
• When updating the registers by using the ST bit the following must be taken into account: The new value
is written into the registers with the rising edge of the RUN bit. This RUN bit is clocked by the RTC clock
(32 kHz, 100kHz, 2MHz or 4 MHz depending on device and mode). To make sure that the update is done
properly, write the new values into the registers, set ST to 0, wait for the RUN bit to go low and then start
the circuit again by setting ST to 1. RUN will go low at the second rising edge of the RTC clock after ST
has been set to 0. It will rise again at the half second rising edge of RTC clock after ST has been set to 1.
If this operation is to be done several times directly after each other, wait for RUN to go to high before
setting ST to low again.
• If a reload has occurred during updating the sub-second registers, WTBRL0, WTBRH0, WTBR1, an
unexpected value may be reloaded to the 21 bit down counter. Therefore, it is recommended that the sub-
second register, WTBR, should be updated with the start bit (WTCR:ST) set to "0".
• If all the sub-second registers, WTBRL0, WTBRH0, WTBR1, are set to "0", the 21 bit down counter does
not operate, resulting in the Real-time Clock module to be inoperational.
• If a carry has occurred during reading from the hour/minute/second registers, WTHR/WTMR/WTSR,
inappropriate values may be read. To avoid this, it is recommended that interrupts (INT0-4) should be
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MB96300 Super Series Hardware Manual