Fujitsu MB96300 series Hardware Manual page 285

MB96300 Super Series Hardware Manual
10.4.2 Operations of Sub Clock Timer
The Sub clock timer functions as an interval timer for generating interrupts at specified
intervals and as a timer for waiting for the Sub oscillation to stabilize.
■ Sub clock counter
The Sub clock counter consists of a 17-bit counter that is clocked with the Sub clock CLKSC. When the Sub
clock is active, the Sub clock counter always keeps counting.
The Sub clock counter is cleared when the Sub clock is stopped (transition to Stop mode or Sub clock
disabled with CKSR: SCE bit and confirmed by the CKMR: SCM bit), by writing "0" to the SCTR bit of the
SCTCR register, by a Power reset, an External reset and by a Sub clock stop detection reset.
Note:
The Sub clock counter is cleared and stopped as long as the External reset is asserted. Hence the Sub
clock stabilization time is delayed by RST and starts counting after deasserting the External reset. This
behavior differs from the Main clock counter.
■ Interval interrupt function
Interrupts are generated at specified intervals according to the carry signals of the Sub clock counter. The
SCTIF flag is set at the intervals specified with the SCTI[2:0] bits of the SCTCR register. The interval time
starts when the Sub clock timer is cleared and starts counting.
When the Sub clock is stopped (transition to Stop mode or Sub clock disabled with CKSR: SCE bit and
confirmed by the CKMR: SCM bit), the Sub clock timer is used as a timer for waiting for the Sub oscillation
to stabilize upon recovery. Therefore, the Sub clock counter is immediately cleared when the Sub clock is
stopped.
CHAPTER 10 SOURCE CLOCK TIMERS
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