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MB96300 Super Series Hardware Manual
4.2.1
DMA Interrupt Request Select Register (DISEL)
Each DMA channel has one Interrupt Request Select Register (DISEL0 ... DISEL15). This
register defines which IRQ number is used to trigger the DMA transfer on this channel.
■ DMA Interrupt Request Select Register (DISEL)
Figure 4.2-2 DMA Interrupt Request Select Register (DISEL) configuration
Address:
0x380...38F
Read/Write:
Initial Value:
R/W:
[bit 7 to 0] IS: Interrupt select
For each DMA channel a DISELx register exists, which defines the IRQ number to trigger the DMA
transfer on this channel. The valid range of the selectable IRQ number is from 12 to a device dependent
maximum number. Only hardware interrupts can trigger DMA operation.
Note:
DISEL can be read and written.
The DISEL register is undefined after reset.
At read operation, DISEL registers of not available channels return undefined value.
Write operations to DISEL registers of not available channels have no effect.
Do not configure the same interrupt number in more than one enabled DMA channel.
When updating a DISEL register ensure that the associated IRQ is deactivated or the DMA channel is
disabled.
07
06
05
IS7
IS6
IS5
(R/W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
0
0
0
readable and writable
04
03
02
01
00
IS4
IS3
IS2
IS1
IS0
0
1
1
0
CHAPTER 4 DMA
Bit No.
DISEL0...15
0
121
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