I 2 C Interface Operation - Fujitsu F2MC-16LX Hardware Manual

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CHAPTER 22 I C INTERFACE
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22.3 I C Interface Operation
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For I C bus, 1 serial data line (SDA), 1 serial clock line (SCL), and 2 bidirectional bus
lines are responsible for communication. I
output pins (SDA and SCL) to them, allows wired logic.
Start Condition
If "1" is written to MSS bit in the state of the bus being released (BB=0 and MSS=0), I
generates the start condition as soon as it changes to the master mode. In the master mode the start
condition can be regenerated by writing "1" to SCC bit even though the bus is in use (BB=1). To generate
start conditions, 2 methods are provided as follows.
• Writing "1" to MSS bit in the state that the bus is not in use (MSS=0 * BB=0 * INT=0 * AL=0).
• Writing "1" to SEC bit in the state of interrupting in bus master (MSS=1 * BB=1 * INT=1 * AL=0).
When the bus (in the idle state) is used by other systems and if "1" is written to MSS bit, then AL bit is set
to "1". Writing to MSS bit and SCC bit in any other state than being mentioned above is ignored.
Stop Condition
When "0" is written to MSS bit in the state of the master mode (MSS=1), the stop condition is generated,
resulting in the slave mode. The condition to generate the stop condition is as follows.
Writing "0" to MSS bit in the state of interrupting in bus master (MSS=1 * BB=1 * INT=1 * AL=0).
Writing "0" excluding this in the MSS bit is disregarded.
Addressing
In the master mode, BB= "1" and TRX= "1" will be set after the start condition generation, and it outputs
the IDAR register contents from the MSB. After sending the address data, receives the acknowledgement
from the slave, reverses bit 0 (bit 0 of IDAR register that is already sent) of the sending data, and then
stores it into TRX bit.
In the slave mode, BB is set to "1" and TRX is set to "0" after the start condition is generated, and the
sending data from the master is received in IDAR register. After the address data is received, IDAR register
is compared with IADR register. If they matches, AAS is set to "1" and the acknowledgement is sent to the
master. Then, bit 0 of the receiving data (bit 0 of IDAR register that is already received) is stored in TRX
bit.
Arbitration
If other master are sending the data simultaneously in the master sending mode, the arbitration will occur.
When the sending data of its own is "1", and the data on SDA line is "L" level, it is considered that its
arbitration is lost and AL is set to "1". When an attempt is made that the start condition is generated in the
state the bus is in use as mentioned above, Al is also set to "1".When AL is set to "1", MSS is 0 and TRX is
"0", resulting in the slave receiving mode.
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C interface, which has 2 open drain input-
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C interface