Fujitsu MB96300 series Hardware Manual page 743

F2mc-16fx 16-bit

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EP1 to EP5 control registers (EP1C to EP5C) must always be set, except DMAE, NULE, and STAL

bits, when both UDCC:RST bit and EP[0..5]S:BFINI are 1. Those registers must not be overwrite

while the USB is operating.

Below a description of the function of each bit in the EP1 to EP5 control register (EP1C to EP5C).

• Endpoint enable. Setting the EPEN bit allows it to be configured

by the host as an end point for use in the USB Function. TYPE,

DIR, and PKS of the EP1 to EP5 control registers become ready

for configuration.

• Transfer/Endpoint type.

• This bit specifies the transfer direction of the endpoint

• DMA enable bit. If enabled, the DMA handles automatically the

transmission and reception of transfered data. Cf 30.4.5 for

• Access to transmit and receive buffers by CPU is forbidden

while the DMAE bit is set. Set the number of DMA transfer data

to a multiple of the value of the PKS set in direction the EP1 to

EP5 control registers (EP1C to EP5C) when transferring data to

• Enable NULL transfer. Cf 30.4.6 for details.

• NULE bit has no effect on communications when transferring

data to OUT direction and when the automatic buffer transfer

mode is disabled.

• Set the endpoint in STALL status (STALL response).

• STALL keeps responding for HOST while setting the STAL bit.

The USB Function can return from STALL status with the

ClearFutcher command from the host after the STAL bit was

• Reserved for EP2 to EP5

CHAPTER 29 USB FUNCTION