MB96300 Super Series Hardware Manual
APPENDIX C Timing Diagrams in Flash Memory Mode
Each timing diagram for the external pins of the Flash devices in MB96300 Super series
during Flash Memory mode is shown below.
■ Data read by read access
AQ16 to AQ0
CE
OE
WE
DQ7 to DQ0
Figure C-1 Timing diagram for read access
Address stable
t
ACC
t
OEH
t
CE
High impedance
APPENDIX C Timing Diagrams in Flash Memory Mode
t
RC
t
OE
Output defined
t
DF
t
OH
High
impedance
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