Oscillation Stabilization Wait Time - Fujitsu MB96300 series Hardware Manual

6.5

Oscillation Stabilization Wait Time

When the power is turned on, when stop mode is released or when a disabled clock is
enabled, an oscillation stabilization wait time is required before the clock can be used.
■ Oscillation Stabilization Wait Interval
Ceramic and crystal oscillators which can be connected to the X0/X1 and X0A/X1A pins generally require
several ms to stabilize at their natural frequency (oscillation frequency) when oscillation starts. The internal
PLL multiplier circuit and the RC oscillator also need a certain stabilization time after activation. For this
reason, CPU operation with the activated clock is not allowed immediately after oscillation starts but is
allowed only after full oscillation stabilization.
After the oscillation stabilization wait interval has elapsed, the corresponding clock ready monitor bit will
be set and the clock can be selected as System clock.
Because the oscillation stabilization time of the Main and Sub oscillator depends on the type of oscillator
(crystal, ceramic, etc.), the proper oscillation stabilization wait interval for the oscillator used must be
selected. An oscillation stabilization wait interval is selected by setting the Clock Stabilization Select
Register (CKSSR). The stabilization time of the RC oscillator is fixed and the stabilization time of the PLL
can be selected depending on the PLL and main clock frequency.
When the clock source is switched, the MCU runs with the previously selected clock until the newly
selected clock is stabilized. When the corresponding clock ready flag is set, the MCU changes to the
specified clock.
A Power reset or External reset clears all source clock timers and clock ready monitor bits and the
corresponding oscillation stabilization wait interval is applied.
Software and Watchdog resets do not affect the source clock timers and Main and Sub clock monitor bits
(no Main/Sub oscillation stabilization wait interval applied if clock was enabled before reset), but clear the
RC and PLL clock monitor bits (PLL is disabled and RC oscillation stabilization time is applied).
Clock stop resets clear the source clock timer and clock monitor bit of the clock that caused the reset. This
clock should not be used any more. The PLL is also disabled and the RC oscillation stabilization time
applied.
Figure 6.5-1"Operation Immediately after Oscillation Starts" shows the operation of the oscillators directly
after activation.
CHAPTER 6 CLOCKS
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