Fujitsu MB96300 series Hardware Manual page 258

F2mc-16fx 16-bit

Hide thumbs Also See for MB96300 series:

Table of Contents

CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT

CPU operation

Return by an interrupt

If an NMI interrupt is asserted or if an External interrupt generates an interrupt request of higher than level

seven during Stop mode, the Stop mode is released and the MCU returns to the Run mode selected by the

SC1S System Clock 1 Select bits (after applying the appropriate clock stabilization wait time). Oscillators are

enabled according to the configuration of the CKSR register. After the Stop mode is released, the interrupt is

handled as an ordinary interrupt.

If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), the

interrupt level mask register (ILM) and interrupt control register (ICR), then the CPU finishes the last

instructions which were stored in the pipeline and then executes the interrupt routine. After return from this

interrupt, the CPU executes the instruction following the last instruction executed before entering the

interrupt routine.

If the interrupt is not accepted, the CPU directly executes the instruction following the last instruction

executed before entering the Stop mode.

Figure 9.4-6 "Release of Stop Mode by Interrupt" shows the release of a Stop mode when an interrupt occurs

Interrupt from peripheral function

Set the enable ﬂag

Enable oscillators and PLL according

to RCE, MCE, PCE and SCE bits and

wait for stabilization of clock selected

by SC1S bits. This clock is always activated

independent of the corresponding enable bit

Figure 9.4-5 Release of the Stop Mode by External Reset

Stop mode release

Figure 9.4-6 Release of Stop Mode by Interrupt

INT occurrence?

(IL smaller than 7)

Interrupt is executed

Reset sequence Execution

Reset cleared and RC clock ready

Stop mode is not released

Next instruction is executed

MB96300 Super Series

Stop mode is

not released

Stop mode is