Fujitsu MB96300 series Hardware Manual page 654

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CHAPTER 24 REAL TIME CLOCK
bit1: Output Enable
OE
0
The WOT external pin can be used as a general purpose I/O or for another peripheral
block.
1
The WOT external pin serves as the output for the 21-bit down counter.
bit0: Start
ST
0
The Real-time Clock module stops to operate, and the 21 bit down counter and the hour/
minute/second counters are cleared.
1
The settings of the hour/minute/second registers are loaded to the hour/minute/second
counters, and the Real-time Clock module starts to operate.
Application Notes:
The Sub-second register of the RTC module stores the reload value for the 21bit counter. This value is
reloaded after the reload counter reaches "0". When modifying all three bytes, make sure the reload operation
will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the incorrect
value of the combination of new data and old data bytes. It is generally recommended that the Sub-Second
register is updated while the ST bit is "0".
However, if this update is done immediately after an RTC second interrupt, there should be enough time to
securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to
"0" and the module is in operation.
When updating the registers by using the ST bit the following must be taken into account:
The new value is written into the registers with the rising edge of the RUN bit. This RUN bit is clocked by
the RTC clock (main clock, sub-oscillator clock or RC clock depending on device and mode). To make sure
that the update is done properly, write the new values into the registers, set ST to 0, wait for the RUN bit to
go low and then start the circuit again by setting ST to 1. RUN will go low at the second rising edge of the
RTC clock after ST has been set to 0. It will rise again at the half second rising edge of RTC clock after ST
has been set to 1. If this operation is to be done several times directly after each other, wait for RUN to go to
high before setting ST to low again.
■ Timer Control Extended Register (WTCER)
Timer Control Extended Register
Initial value:
R/W : Readable and writable
Note:
WTCER is initialized by all reset causes except for unused bits.
bit7-2: Undefined
Writing does not affect the operation. The read value is undefined. Read-modify-write is not affected.
646
Status/Operation
Figure 24.2-3 Timer Control Extended Register (WTCER)
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
-
: Undefined
X : Undefined value
MB96300 Super Series Hardware Manual
Operation
2
1
0
-
INTE4 INT4
WTCER
-
R/W
R/W
X
0
0

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