Fujitsu MB96300 series Hardware Manual page 119

MB96300 Super Series Hardware Manual
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INTE (System reserved, only available with DSU)
INTE is used to insert a software break point for the debug system, using the in circuit emulator (ICE). At
insertion of a software instruction break, the first byte of the original instruction is replaced by INTE.
This instruction branches to the interrupt processing routine indicated by a fixed vector defined by the DSU.
The PC value saved in the stack is the address at which INTE is stored. Executing the RETI instruction in the
interrupt routine restores the processing at this location (INTE can be replaced by the original instruction at
removal of the software break point).
The privileged mode flag (P flag) is cleared and the ILM register is set to 2 (enters level P2). This disables all
hardware interrupts and exceptions. The P flag and ILM are restored at execution of the RETI instruction.
Operation:
(SSP)<-(SSP)-2, ((SSP))<-(AH)
(SSP)<-(SSP)-2, ((SSP))<-(AL)
(SSP)<-(SSP)-2, ((SSP))<-(DPR):(ADB)
(SSP)<-(SSP)-2, ((SSP))<-(DTB):(PCB)
(SSP)<-(SSP)-2, ((SSP))<-(PC)
(SSP)<-(SSP)-2, ((SSP))<-(PS)
(S)<-1, (I)<-0, (P)<-0, (ILM)<-2
(PCB)<-Fixed vector from DSU (upper byte, 00
(PC)<-Fixed vector from DSU (lower word, 0400
Without the DSU, INTE is handled same as the undefined instruction exception. Interrupt vector #10 is
referenced. The P flag is not cleared and ILM is not updated.
■ Hardware exceptions (non maskable interrupts)
Hardware exceptions are external events, which are not maskable by any software instruction. Hardware
exceptions with a higher level number, than the actual processed one, are suspended until execution of the
RETI instruction restores the previous level. In addition, hardware exceptions disable any hardware interrupt
acceptance.
At occurrence of multiple hardware exceptions at the same time, they will be accepted with following
priority: VEIB > VENMI > NMI > HW-INT9. If the current interrupt level mask and P flag setting allows it,
hardware exceptions are accepted at the end of each instruction execution and during execution of string
instructions.
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HW-INT9
HW-INT9 is used by the address match detection function. With that function embedded debug support
(operand address break or data value break) or a simple memory protection can be provided.
The privileged mode flag (P flag) is cleared and ILM is set to 6 (enters level P6). This disables all hardware
interrupts from peripherals. The P flag and ILM are restored at the execution of the RETI instruction.
Operation:
(SSP)<-(SSP)-2, ((SSP))<-(AH)
(SSP)<-(SSP)-2, ((SSP)<-(AL)
(SSP)<-(SSP)-2, ((SSP))<-(DPR):(ADB)
(SSP)<-(SSP)-2, ((SSP))<-(DTB):(PCB)
CHAPTER 3 INTERRUPTS
, address is ignored by DSU)
H
, address is ignored by DSU)
H
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