Fujitsu MB96300 series Hardware Manual page 491

MB96300 Super Series Hardware Manual
■ Serial status register (SSRn)
Figure 20.4-4 Configuration of the serial status register (SSRn)
15
R/W : Readable and writable
R : Flag is read only, write to it has
no effect
: Initial value
n = 0...9 according to device ( Please refer to
the datasheet of the corresponding device)
Table 20.4-3 Functions of each bit of status register (SSRn)
Bit name
bit15 PE:
Parity error flag bit
14 13 12 11 10 9
R R R R R R/W R/W R/W
• This bit is set to 1 when a parity error occurs during reception at PE=1.
• It is cleared when 1 is written to the CRE bit of the serial control register (SCRn).
• In Mode 3, it is also cleared when ESCRn:LBD = 1.
• A receive interrupt request is output when this bit and the RIE bit are 1.
• Data in the reception data register (RDRn) is invalid when this flag is set.
8
SSRn
Initial value
0 0 0 0 1 0 0 0
B
bit8
TIE Transmission Interrupt enable
0 Disables Transmission Interrupt
1 Enables Transmission Interrupt
bit9
RIE Reception Interrupt enable
0 Disables Reception Interrupt
1 Enables Reception Interrupt
bit10
BDS Bit direction setting
0 send / receive LSB first
1 send / receive MSB first
bit11
TDRE Transmission data register empty
0 Transmission data register is full
1 Transmission data register is empty
bit12
RDRF Reception data register full
0 Reception data register is empty
1 Reception data register is full
bit13
FRE
0 No framing error occurred
1 A framing error occurred during reception
bit14
ORE
0 No overrun error occurred
1 An overrun error occurred during reception
bit15
PE
0 No parity error occurred
1 A parity error occurred during reception
Function
CHAPTER 20 USART
Framing error
Overrun error
Parity error
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