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MB96300 Super Series Hardware Manual
■ Structure of the Memory Patch Function
address and control
Patch Address
PFA0
Patch Address/Mask
PFA1
Access Type Match
PFCS
Patch Enable bit
PFCS:PE
data
Patch Data
PFD0
Patch Data/Mask
PFD1
Match Indication
PFCS:I
Interrupt Enable bit
PFCS:IE
The Memory Patch Function (MPF) has 8 channels, which can be used independently for 8 single address
points or grouped for 4 address ranges. Figure 31.1-1 "Block diagram of the Memory Patch Function" shows
the structure of the MPF.
Each channel of the MPF has a patch function address register (PFAx), a patch data register (PFDx) and a
common patch function control/status register (PFCSx) for a group of 2 channels. Each channel has an
address match indication flag (I), an interrupt enable bit (IE) and a patch enable bit (PE) in the PFCSx. Each
group of two channels has a common address mask (AM) and a common address range (AR) control bit. In
addition there is one byte configuration data to match a specific access type for each group of two channels
(READ, WRITE, BYTE, WORD, CODE, DATA, CPU, DMA).
Figure 31.1-1 Block diagram of the Memory Patch Function
Address
and Type
Match
Detection
Data Match
Detection
set
CHAPTER 31 MEMORY PATCH FUNCTION
address
match
IE
PE
PE
0
1
data
address and
match
data value match
I
IE
EDSU_EN
F2MC−16FX
Core
patch
read
0
data
1
INT9
(hardware IRQ)
817
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