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MB96300 Super Series Hardware Manual
22.8.4
Interrupt Pending Registers (INTPND1n, INTPND2n)
The Interrupt Pending Registers (INTPND1n, INTPND2n) indicate whether a message
object caused an interrupt or not.
■ Interrupt Pending Registers (INTPND1n, INTPND2n)
Figure 22.8-4 Configuration of Interrupt Pending Registers (INTPND1n, INTPND2n)
Int Pending Register 1 high byte
Address : Base + 0xA1
Default value⇒
Int Pending Register 1 low byte
Address : Base + 0x A0
Default value⇒
Int Pending Register 2 high byte
Address : Base + 0xA3
Default value⇒
Int Pending Register 2 low byte
Address : Base + 0x A2
Default value⇒
■ Function of Interrupt Pending Registers (INTPND1n, INTPND2n)
INTPND32-1
Interrupt Pending Bits (of all Message Objects)
0
This message object is not the source of an interrupt.
1
This message object is the source of an interrupt.
These registers hold the INTPND bits of the 32 Message Objects. By reading out the INTPND bits, the CPU
can check for which Message Object an interrupt is pending. The INTPND bit of a specific Message Object
can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after
reception or after a successful transmission of a frame. This will also affect the value of INTID in the
Interrupt Register INTRn.
15
14
H
Read/write ⇒
(R)
(R)
(0)
(0)
7
6
H
Read/write ⇒
(R)
(R)
(0)
(0)
15
14
H
Read/write ⇒
(R)
(R)
(0)
(0)
7
6
H
Read/write ⇒
(R)
(R)
(0)
(0)
CHAPTER 22 CAN CONTROLLER
13
12
11
10
INTPND16-9
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
INTPND8-1
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
13
12
11
10
INTPND32-25
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
INTPND24-17
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
⇐ Bit no.
9
8
INTPND1Hn
(R)
(0)
⇐ Bit no.
1
0
INTPND1Ln
(R)
(R)
(0)
(0)
⇐ Bit no.
9
8
INTPND2Hn
(R)
(0)
⇐ Bit no.
1
0
INTPND2Ln
(R)
(R)
(0)
(0)
617
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