Explanation Of I 2 C Interface Operation - Fujitsu FR60 Hardware Manual

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CHAPTER 15 I C INTERFACE
15.3 Explanation of I
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The I C bus consists of two bidirectional bus lines used for transfer: one serial data line
(SDA) and one serial clock line (SCL). The I
drain I/O pins (SDA and SCL), enabling wired logic.
■ START Condition
Write "1" to the MSS bit while the bus is open (BB=0, MSS=0) to place the I
and to generate a START condition. The interface sends the value of the IDAR register as a slave address.
Write "1" to the SCC bit while the interrupt flag is set in bus master mode (IBCR MSS =1, INT = 1) to
generate a repeated START condition.
Write "1" to the MSS bit while the bus is busy (IBSR BB = 1, TRX = 0, IBCR MSS = 0 or INT = 0) to
release the bus and start transmission.
If a write (reception) access is performed in slave mode, the interface starts transmission after transmission
is completed and the bus is released. If the interface is sending data, it does not start transmission even
though the bus has been released.
The interface must be checked for the following:
• Whether the interface is specified as a slave (IBCR MSS=0, IBSR AAS=1)
• Whether data byte transmission is normal (IBSR AL=1) when the next interrupt is received
■ STOP Condition
Write "0" to the MSS bit in master mode (IBCR MSS = 1, INT = 1) to generate a STOP condition and to
place the interface in slave mode. Writing "0" to the MSS bit in any other state is ignored.
After the MSS bit is cleared, the interface attempts to generate a STOP condition. However, a STOP
condition will not be generated if the SCL line is driven to "L". An interrupt is generated after the next byte
is transferred.
Note:
After "0" is written to the MSS bit, it takes time until a STOP condition is generated. If the I
interface is disabled (IDAR DBL = 1 or ICCR EN = 0) before the STOP condition is generated, the
operation stops immediately and an incorrect clock is generated on the SCL line.
Disable the I
been generated (IBSR BB = 0).
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C Interface Operation
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C interface (IDAR DBL = 1 or ICCR EN = 0) after checking that a STOP condition has
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C interface has two corresponding open-
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C interface in master mode
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C