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MB96300 Super Series Hardware Manual
14.4.2
Control Status Registers of Output Compare (OCS(2n) /
OCS(2n+1))
The Control Status Register (OCS(2n) / OCS(2n+1)) sets the operation mode of output
compare, starts and stops output compare, controls interrupts, and sets the external
output pins.
■ Output Compare Control Status Register (OCS(2n))
Figure 14.4-3 Output Compare Control Status Register (OCS(2n))
R/W R/W R/W R/W
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
:
Initial value
Remark:
The suffix "n" denotes the Output Compare Unit number (0, 1, 2, ...). The register name and the bit names are
composed by the register/bit type name and the suffix. For example:
7
6
5
4
3
2
1
ICE
ICP
ICP
ICE
-
-
CST CST
-
-
R/W R/W
OCS(2n)
0
Initial value
0 0 0 0 X X 0 0
B
bit 0
CST(2n+0)
Comparison with timer for channel (2n+0)
0
Compare operation disabled for channel (2n+0)
1
Compare operation enabled for channel (2n+0)
bit 1
CST(2n+1)
Comparison with timer for channel (2n+1)
0
Compare operation disabled for channel (2n+1)
1
Compare operation enabled for channel (2n+1)
bit 4
ICE(2n+0)
Compare interrupt enable for channel (2n+0)
0
Output compare interrupt disabled for channel (2n+0)
1
Output compare interrupt enabled for channel(2n+0)
bit 5
ICE(2n+1)
Compare interrupt enable for channel (2n+1)
0
Output compare interrupt disabled for channel (2n+1)
1
Output compare interrupt enabled for channel (2n+1)
bit 6
ICP(2n+0)
Compare match status for channel (2n+0)
0
No compare match for channel (2n+0)
1
Compare match for channel (2n+0)
bit 7
ICP(2n+1)
Compare match status for channel (2n+1)
0
No compare match for channel (2n+1)
1
Compare match for channel (2n+1)
CHAPTER 14 16-BIT I/O TIMER
n = 0, 1, 2, 3, ...
377
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