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CHAPTER 6 CLOCKS
Table 6.2-4 Function Description of Each Bit of the Clock Frequency Control Register (CKFCR) (2/2)
Bit name
bit 12 -
PC2D0 to PC2D3:
bit 15
Peripheral Clock 2
Division select bits
162
• These bits control the clock divider for the Peripheral clock (CLKP2) according to
the following table:
bit11
bit10
bit9
PC2D3
PC2D2
PC2D1
PC2D0
0
0
0
0
0
0
0
0
1
...
...
...
1
1
1
1
1
1
• These bits are initialized to "0000" (CLKP2 = CLKS2) by each reset.
Note:
For MB96F348, a correct access to the CAN-RAM cannot be ensured at higher
frequencies. Therefore the clock divider setting CLKP2 = CLKS2 / 2 must be
forbidden (or restricted).
Function
bit8
Peripheral Clock 2 Division select bits
0
CLKP2 is CLKS2 (divided by 1)
1
CLKP2 is CLKS2 divided by 2
0
CLKP2 is CLKS2 divided by 3
...
CLKP2 is CLKS2 divided by PC2D[3:0]
0
CLKP2 is CLKS2 divided by 15
1
CLKP2 is CLKS2 divided by 16
+ 1
B
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