Fujitsu MB96300 series Hardware Manual page 399

MB96300 Super Series Hardware Manual
Table 14.5-2 Input Capture Unit Control Status Register bits
Bit name
bit7 ICP(2n+1):
Interrupt request flag
bit (Input capture
2n+1)
bit6 ICP(2n):
Interrupt request flag
bit (Input capture 2n)
bit5 ICE(2n+1):
Interrupt request
enable bit (Input
capture 2n+1)
bit4 ICE(2n):
Interrupt request
enable bit (Input
capture 2n)
bit3/2 EG(2n+1)1,
EG(2n+1)0
bit1/0 EG(2n)1, EG(2n)0
The suffix n = 0, 1, 2, 3, ... denotes the Input Capture Unit number. The bit names are composed by their type name and the
suffix. Hence, for
n = 0: ICP1, ICP0, ICE1, ICE0, EG11, EG10, EG01, EG00
n = 1: ICP3, ICP2, ICE3, ICE2, EG31, EG30, EG21, EG20 etc.
■ Input Capture Unit Edge Register (ICE(2n)(2n+1))
The Input Capture Unit Edge Register (ICE(2n)(2n+1)) contain device dependent configuration bits. These
registers are described in Chapter 1.6 "Input Capture Unit source select for LIN-USART".
• This bit is used as interrupt request flag for Input Capture Unit n, second
channel.
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICE(2n+1)) is set, an interrupt can be generated
upon detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This bit is used as interrupt request flag for Input Capture Unit n, first channel.
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICE(2n)) is set, an interrupt can be generated
upon detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This bit is used to enable input capture interrupt request for Input Capture Unit
n, second channel.
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP(2n+1)) is set.
• This bit is used to enable input capture interrupt request for Input Capture Unit
n, first channel.
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP(2n)) is set.
• These bits are used to specify the valid edge polarity of an external input for
Input Capture Unit n, second channel
• These bits are also used to enable input capture operation
• These bits are used to specify the valid edge polarity of an external input for
Input Capture Unit n, first channel.
• These bits are also used to enable input capture operation
CHAPTER 14 16-BIT I/O TIMER
Function
391