Fujitsu MB96300 series Hardware Manual page 577

MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE
the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR register.
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