Table of Contents
Advertisement
MB96300 Super Series Hardware Manual
Table 14.3-1 Control status register of Free-Running-Timer (TCCSLn)
Bit name
bit 7
IVF
bit 6
IVFE
bit 5
STOP
bit 4
MODE
bit 3
CLR
bit 2 to
CLK2, CLK1, CLK0
0
• This bit is the interrupt request flag bit and clear bit
• Writing "0": A possible interrupt is cleared.
• Writing "1": No effect.
• "1" is always read during a read-modify-write cycle.
• This bit is set to "1" if the Free Running Timer overflows or if the timer value
matches with the compare register 0 or compare register 4 and the MODE bit is set
to "1".
• This bit enables the interrupt request
• Writing "0": Interrupt disabled.
• Writing "1": Interrupt enabled.
• The STOP bit is used to stop the timer.
• Writing "0": Counter enabled (operation).
• Writing "1": Counter disabled (stop).
• "0": Initialization by reset or clear bit
• "1": Initialization by reset, clear bit, or compare register 0 or compare register 4
• The CLR bit initializes the operating Free-Running Timer to the value "0000"
• Writing "0": no effect.
• Writing "1": Counter is initialized.
Note:
To initialize the counter value while the timer is stopped (STOP = 1), write "0000"
to the data register (TCDT).
These bits are used to select the count clock for the 16-bit-Free-Running Timer. The
clock is updated immediately after a value is written to these bits. Therefore, ensure
that the input capture and output compare operations are stopped before a value is
written to these bits.
Count
CLK2
CLK1
CLK0
0
0
0
0
0
1
0
1
0
0
1
1
Φ / 16
1
0
0
Φ / 32
1
0
1
Φ / 64
1
1
0
Φ / 128
1
1
1
CHAPTER 14 16-BIT I/O TIMER
Function
Φ = 20
Φ = 16
clock
MHz
MHz
Φ
50 ns
62.5 ns
Φ / 2
100 ns
125 ns
Φ / 4
0.2 µs
0.25 µs
Φ / 8
0.4 µs
0.5 µs
0.8 µs
1 µs
1.6 µs
2 µs
3.2 µs
4 µs
6.4 µs
8 µs
Φ = 8
Φ = 4
Φ = 1
MHz
MHz
MHz
0.25 µs
1 µs
125 ns
0.25 µs
0.5 µs
2 µs
0.5 µs
1 µs
4 µs
1 µs
2 µs
8 µs
2 µs
4 µs
16 µs
4 µs
8 µs
32 µs
8 µs
16 µs
64 µs
16 µs
32 µs
128 µs
371
Advertisement
Table of Contents
