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CHAPTER 22 CAN CONTROLLER
are transmitted, the TXRQST and NEWDAT bits will be reset and, if enabled by TXIE, INTPND will be
set.
[bit4]
res
[bit3]
EIE
0
1
[bit2]
SIE
0
1
[bit1]
IE
0
1
[bit0]
INIT
0
1
Note:
The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or
resetting INIT. If the device goes busoff, it will set INIT of its own accord, stopping all bus activities.
Once INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 *
11 consecutive recessive bits) before resuming normal operation. At the end of the busoff recovery
sequence, the Error Management Counters will be reset.
Note:
During the waiting time after the resetting of INIT, each time a sequence of 11 recessive bits has been
monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up
whether the CAN bus is stuck at dominant level or continuously disturbed and to monitor the proceeding
of the busoff recovery sequence.
588
reserved bit
Always write "0". Read value is not defined. Read-Modify-Write is not affected.
Error Interrupt Enable
Disabled - No Error Status Interrupt will be generated.
Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt.
Status Change Interrupt Enable
Disabled - No Status Change Interrupt will be generated.
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus
error is detected.
Module Interrupt Enable
Disabled - Module Interrupt is always inactive.
Enabled - Interrupts will be generated. The request remains active until all pending interrupts are pro-
cessed.
Initialization
Normal Operation
Initialization is started.
MB96300 Super Series Hardware Manual
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