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CHAPTER 34 MASK-ROM MEMORY INTERFACE
Address:
0003F2
H
7
SSE WEXL CLKBW ADS
R/W R/W R/W R/W R/W
Table 34.2-2 ROM timing configuration register (MFMTC0)
Bit name
bit 0 -
FAWC0 to
bit 2
FAWC2
bit 3 -
-
bit 7
894
Figure 34.2-2 ROM timing configuration register 0 (MFMTC0)
6
5
4
3
2
1
SYNC
FAWC2 FAWC1 FAWC0
R/W R/W R/W
•
These bits define how many CPU wait states (in number of CLKB cy-
cles) are added at any read access to the ROM.
•
These bits have to be set depending on the CLKB frequency.
•
The initial value is "001".
•
Only available for compatibility with Flash interface but without func-
tionallity. Any values can be writen here.
0
Initial value
0 0 1 1 1 0 0 1
bit2
bit1
bit0
FAWC2
FAWC1
FAWC0
0
0
0
0 wait cycles
0
0
1
1 wait cycles
0
1
0
2 wait cycles
0
1
1
3 wait cycles
1
0
0
4 wait cycles
1
0
1
5 wait cycles
1
1
0
6 wait cycles
1
1
1
7 wait cycles
bit3
SYNC
0
value has no effect
1
value has no effect
bit4
ADS
0
value has no effect
1
value has no effect
bit5
CLKBW
0
value has no effect
1
value has no effect
bit6
WEXL
0
value has no effect
1
value has no effect
bit7
SSE
0
value has no effect
1
value has no effect
Function
B
Flash Access Wait Cycles
Flash compatibility
Flash compatibility
Flash compatibility
Flash compatibility
Flash compatibility
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