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■ Block Diagram
The following block diagram shows the clock sources, the generation of the internal clocks and the source
clock timers of the F2MC-16FX MCU. The different clocks are described below. See also CHAPTER 1
OVERVIEW for a block diagram showing which modules are connected to which clocks.
Figure 6.1-1 Block diagram of the clock generation and source clocks timers
PLL configuration
X0 Pin
Main oscillation
circuit
X1 Pin
X0A Pin
Sub oscillation
circuit
X1A Pin
RC oscillation
circuit
RCFS
Frequency selection
See datasheet for support of CLKP3.
PLL multiplier
circuit
(mul-1 to mul-32)
Main Clock Timer
Sub Clock Timer
RC Clock Timer
SC2S[1:0]
System Clock
2 Selector
PC2D[3:0]
Peripheral Clock
2 Divider
CLKP2
(div-1 to div-16)
(clocking peripheral
bus 2)
PC3D[3:0]
Peripheral Clock
3 Divider
CLKP3
(div-1 to div-16)
(clocking peripheral
bus 3)
CLKPLL
Clock Modulator
CLKS2
BCD[3:0]
Bus Clock
Divider
(div-1 to div-16)
PC1D[3:0]
Peripheral Clock
1 Divider
(div-1 to div-16)
CHAPTER 6 CLOCKS
Clock modulator
configuration
CLKMOD
Clock
modulator
enable
CLKMC
CLKSC
CLKRC
SC1S[1:0]
System Clock
1 Selector
CLKS1
CLKB
(clocking core bus)
CLKP1
(clocking peripheral
bus 1)
145
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