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CHAPTER 20 USART
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Transmission operation
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSRn) is "1",
transmission data is allowed to be written to the Transmission Data Register (TDRn). When data is written,
the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control
Register (SCRn), the data is written next to the transmission shift register and the transmission starts at the
next clock cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes "1", so that new
data can be written to the TDRn.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the
initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur
immediately.
When the character length is set to 7 bits (CL=0), the unused bit of the TDRn is always the MSB,
independently from the bit direction setting in the BDS bit (LSB first or MSB first).
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Reception operation
Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCRn. If
a start bit is detected, a data frame is received according to the format specified by the SCRn. In case of
errors, the corresponding error flags are set (PE, ORE, FRE). After the reception of the data frame the data is
transferred from the serial shift register to the Reception Data Register (RDRn) and the Receive Data
Register Full (RDRF) flag bits of SSRn and ESIRn registers are set.
If receive interrupt is enabled (RIE = 1) and ESIRn:AICD = "0", the interrupt is generated by SSRn:RDRF.
If receive interrupt is enabled (RIE = 1) and ESIRn:AICD = "1", the interrupt is generated by ESIRn:RDRF.
The data then has to be read by the CPU. By doing so, the SSRn:RDRF flag is cleared.
When ESIRn:AICD = "0", this also clears the interrupt.
When ESIRn:AICD = "1", the interrupt mst be cleared by writing "1" to ESIRn:RDRF.
When the character length is set to 7 bits (CL=0), the unused bit of the RDRn is always the MSB,
independently from the bit direction setting in the BDS bit (LSB first or MSB first).
Note:
Only when the RDRF flag bit is set and no errors have occurred the Reception Data Register (RDRn)
contains valid data.
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Used clock
Use the internal clock or external clock. Select the baudrate generator (SMRn:EXT = 0 or 1, SMRn:OTO =
0) for desired baudrate.
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Stop bit, error detection, and parity:
Number of stop bit, 1 or 2 can be specified by the SBL bit of the SCRn register. When receiving and 2-bit is
specified as the stop bit, the second stop bit is checked in addition to the first stop bit. The RBI (bus idle) flag
is set after the second stop bit. However the RDRF flag is set when the first stop bit is received. In mode 0,
parity error, overrun error and framing error are checked. In mode 1, parity check is not supported and
overrun error and framing error are checked. The PEN bit of the SCRn register enables/disables the parity bit
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MB96300 Super Series Hardware Manual
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