Fujitsu MB96300 series Hardware Manual page 563

MB96300 Super Series Hardware Manual
and "0" to the MSS bit, the MSS bit clearing takes priority. A stop condition is generated and the interface
enters slave mode. If specific conditions are met, the AL (arbitration lost) bit does not set the INT
(interrupt) bit. Those conditions are presented in Figure 21.2-4 and Figure 21.2-5.
●
Case 1: When SCL and SDA signals are kept at "L";
The AL bit is set immediately after the MSS bit set to "1" while the BB bit is indicating "0" (no start
condition is detected). However the AL bit will not set the INT bit under this circumstances.
Figure 21.2-4 Diagram of timing at which an interrupt upon detection of "AL bit = 1" does not occur
SCL pin
SDA pin
2
I C operation enable state (EN bit =1)
Master mode setting (MSS bit = 1)
Arbitration lost detection (AL bit = 1)
Bus busy (BB bit)
Interruption (INT bit)
●
Case 2: When I
The interface participates in the I
is set from "0" to "1". In this case the BB bit stays "0" (no start condition is detected) and setting the MSS bit
to "1" results in the AL bit indicating "1". However the AL bit will not set the INT bit under this
circumstances.
SCL pin or SDA pin is Low level.
2
C interface is enabled while there is ongoing communication with another bus master;
2
C bus while the bus is occupied with ongoing communication if the EN bit
CHAPTER 21 400 kHz I2C INTERFACE
"L"
"L"
0
0
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