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CHAPTER 22 CAN CONTROLLER
22.6.4
IFx Arbitration Registers (IFxARB1n, IFxARB2n)
The bits of the Message Buffer registers mirror the Message Objects in the Message
RAM. In case of transmission, the bits of the message arbitration registers (IFxARB1n,
IFxARB2n) specify the ID of the message. In case of reception, the bits of the message
arbitration registers (IFxARB1n, IFxARB2n) specify the acceptance filter.
■ IFx Arbitration Registers (IFxARB1n, IFxARB2n)
Figure 22.6-4 Configuration of the IFx Arbitration Registers (IFxARB1n, IFxARB2n)
IFx Arbitration 1 Register high byte
Address (x = 1): CANn Base + 0x19
(x = 2): CANn Base + 0x49
IFx Arbitration 1 Register low byte
Address (x = 1): CANn Base + 0x 18
(x = 2): CANn Base + 0x 48
IFx Arbitration 2 Register high byte
Address (x = 1): CANn Base + 0x1B
(x = 2): CANn Base + 0x4B
IFx Arbitration 2 Register low byte
Address (x = 1): CANn Base + 0x 1A
(x = 2): CANn Base + 0x 4A
604
15
14
H
H
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Default value⇒
7
H
H
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Default value⇒
15
14
H
XTD
MSGVAL
H
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Default value⇒
7
6
H
H
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Default value⇒
MB96300 Super Series Hardware Manual
13
12
11
10
ID15-8
(0)
(0)
(0)
(0)
6
5
4
3
2
ID7-0
(0)
(0)
(0)
(0)
13
12
11
10
DIR
ID28-24
(0)
(0)
(0)
(0)
5
4
3
2
ID23-16
(0)
(0)
(0)
(0)
⇐ Bit no.
9
8
IFxARB1Hn
(0)
(0)
⇐ Bit no.
1
0
IFxARB1Ln
(0)
(0)
⇐ Bit no.
9
8
IFxARB2Hn
(0)
(0)
⇐ Bit no.
1
0
IFxARB2Ln
(0)
(0)
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