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CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT
9.4.3
Stop Mode
Because this mode causes all oscillators to stop and inactivates all functions, data can
be retained by the lowest power consumption.
■ Functions in Stop Mode
●
CPU, internal memory and data retention
In Stop mode, the clock supplying the CPU and the internal memory (CLKB) is stopped. However the
contents of dedicated registers, such as accumulator, and the internal RAM are retained.
●
Resources
The resource clocks CLKP1 and CLKP2 are stopped and all resources are frozen in their last state.
●
Source clock timers and clocks
The source clock timers (RC clock timer, Main clock timer and Sub clock timer) are all stopped and cleared
together with all oscillators and the PLL. All oscillator ready flags and the PLL ready flag are cleared.
●
Resets and Interrupts
Resets and Interrupts are active in Stop mode and can be used to release the Stop mode.
●
External Bus and Hold function
The external bus is stopped in Stop mode, however the external bus hold function is active (setting external
bus pins to Hi-Z controlled by HRQ pin if hold function is enabled).
●
Status of pins
The SPL bit of the standby mode control register (SMCR) controls whether the external pins in the Stop
mode retain the state they had immediately before switching to the Stop mode or go to the high-impedance
state.
■ Switching to Stop Mode
Writing "11" to the SMS bits of the standby mode control register (SMCR) requests a switch to Stop mode,
independent of the current clock mode. The transition to Stop mode takes place within a few clock cycles
after the request.
Note:
To make sure instructions following the SMS write instruction are executed after wakeup from Stop
mode (and not before transition to Stop mode), poll the SMS bits after setting to "11". Branch to the next
instruction only when the SMS bits are cleared to "00". Reading "11" means that the transition to the Stop
mode has not been performed yet (transition request is still pending).
248
MB96300 Super Series
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