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CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT
Note:
After Stop mode release, the CPU starts operating after stabilization of the System clock 1 selected by the
SC1S bit. However another clock can be selected as System clock 2 with a longer stabilization time. If the
CPU tries to access a peripheral resource clocked by the Peripheral clock 2, then the CPU will be put into
hold state until CLKP2 is stabilized and the access can be completed.
After Stop mode release, the SC2M bits indicate the clock used before stop mode until the newly selected
clock is ready (clock ready monitor bit of clock selected by SC2S bits is "1") because this register can only
be updated with System clock 2.
Note:
Never set the SC1S or SC2S bits to a clock which does not exist (for example "Sub clock mode" when
device has no sub oscillator or no crystal/resonator is connected to sub oscillator pins) because program
execution is delayed until the clock selected by SC1S is stabilized. It is recommended to always select the
RC clock for both System clocks when changing to Stop mode.
If Stop mode is released by reset, the clock mode is always set to RC clock and the reset sequence is executed
after stabilization of the RC oscillator. All registers and functions are reset to the initial state.
●
Clock mode switching
When the clock mode is switched by writing to the SC1S/SC2S bits, do not switch to Sleep or Timer mode
before the clock mode switching is completed. Confirm the completion of clock mode switching by referring
to the SC1M/SC2M bits of the clock monitor register (CKMR).
A transition to Stop mode however is possible without waiting for the clock mode switching.
Only change the setting of the SC1S/SC2S bits when the SMS bits are "00" (no Standby mode transition
request pending).
254
MB96300 Super Series
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