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MB96300 Super Series Hardware Manual
■ Block diagram of Real Time Clock
Oscillation
clock
■ Configuration diagram
Real-Time Clock
RUN WT CR: bit 3
RUN WT CR: bit 3
RUN WT CR: bit 3
Read
Read
Read only
0
0
0
RTC inactive
RT C
RT C
1
1
1
RT C
RT C
RTC active
Oscillation
CLKMC
CLKSC
Prescaler: 1/2
CLKRC
CKSEL WTCKSR: bit10
00
Main Clock
01
Sub Clock
10
RC Clock
ST WT CR: bit 0
ST WT CR: bit 0
ST WT CR: bit 0
0
0
0
Stop after reset
1
1
1
Start
Second Counter
OR
OR
WTSR
(W)
WTSR
UPDT
WT CR: bit 2
0
0
No impact on operation
1
1
Second
Update
Figure 24.1-1 Block diagram of Real Time Clock
Sub-Second
Registers
1/2
1/2
21 Bit
21
Down Counter
Figure 24.1-2 Configuration diagram
WTBR value = 1/2second
(Initial value indeterminate)
WTBR
Reload
21 Bit Counter
Every minute
0
INT1 WT CR: bit10
INT1 WT CR: bit10
INT1 WT CR: bit10
1
0
0
0
Clear interrupt requests
1
1
1
No effect
Every hour
Read: 1=
Read: 1=
Read: 1=Interrupt request has been made
INT2 WT CR: bit12
INT2 WT CR: bit12
INT2 WT CR: bit12
INTE1 WT CR: bit11
INTE1 WT CR: bit11
INTE1 WT CR: bit11
0
0
0
Clear interrupt requests
0
0
0
1
1
1
Disable interrupts
1
1
1
Enable interrupts
Read: 1=
Read: 1=
Read: 1=Interrupt request has been made
Minute Counter
Overflow
Overflow
WTHR
WTMR
(W)
WTMR
(R)
(R)
Minute
h)
Reload
Counter
Second Minute Hour
Update
Second Minute Hour
OE
WTCR: bit 1
0
Disable WOT
1
Enable WOT
0
1
WOT
Every half second
INT4
WT CER: bit0
0
Clear interrupt requests
1
No effect
Read: 1=Interrupt request has been made
Every second
INT0 WT CR: bit8
0
Clear interrupt requests
1
No effect
Read: 1=Interrupt request has been made
0
1
No effect
Every 24 hour (Everyday)
INT3 WT CR: bit14
INT3 WT CR: bit14
INT3 WT CR: bit14
0
0
0
INTE2 WT CR: bit13
INTE2 WT CR: bit13
INTE2 WT CR: bit13
Clear interrupt requests
1
1
1
No effect
0
0
0
Disable interrupts
Read: 1=
Read: 1=
1
1
1
Read: 1=Interrupt request has been made
Enable interrupts
Hour Counter
Overflow
(W)
WTHR
(R)
Hour
CHAPTER 24 REAL TIME CLOCK
INTE4
WT CER: bit1
0
Disable interrupts
1
Enable interrupts
0
1
0
1
INTE0 WT CR: bit9
0
Disable interrupts
1
Enable interrupts
OR
0
1
INTE3 WT CR: bit15
0
Disable interrupts
1
Enable interrupts
RTC
interrupt
641
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