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CHAPTER 19 ALARM COMPARATOR
■ Alarm Comparator Extended Control/Status Register (AECSRn)
Figure 19.2-2 Structure of Alarm Comparator Extended Control/Status register
X
: undefined value
R/W
: readable and writable
Bit 10: ACE (Analog input enable)
0
1
Bit 8: INTREF (Internal Reference voltage select)
0
1
462
15
14
13
12
11
10
9
ACE
-
-
-
-
-
-
-
-
-
-
-
R/W
-
Analog input disabled
Analog input enabled
AVCC/AVSS is selected as Reference voltage. [Initial value]
Internal reference voltage VREF is selected.
MB96300 Super Series Hardware Manual
8
AECSRn
Initial value
INTREF
X X X X X 0 X 0
B
R/W
bit8
INTREF
Internal reference voltage select bit
0
Reference voltage derived from AVCC/AVSS
1
Reference voltage derived from internal reference VREF
bit9
-
Read value is undefined, write always 0
read modify write instructions are not affected
bit10
ACE
Analog input enable bit
0
Analog input disabled
1
Analog input enabled
bit[15:9]
-
Read value is undefined, write always 0,
read modify instructions are not affected
reserved bit
reserved bit
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