Fujitsu MB96300 series Hardware Manual page 255

F2mc-16fx 16-bit

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Table of Contents

MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL

CPU operation

Return by an interrupt

If an NMI interrupt is asserted or if a source clock timer or External interrupt generates an interrupt request

of higher than level seven during a Timer mode, the Timer mode is released and the MCU returns to the

corresponding Run mode (RC Timer -> RC Run, Main Timer -> Main Run, PLL Timer -> PLL Run, Sub

Timer -> Sub Run). After the Timer mode is released, the interrupt is handled as an ordinary interrupt.

If the interrupt is accepted according to the setting of the I flag of the condition code register (CCR), the

interrupt level mask register (ILM) and interrupt control register (ICR), then the CPU finishes the last

instructions which were stored in the pipeline and then executes the interrupt routine. After return from this

interrupt, the CPU executes the instruction following the last instruction executed before entering the

interrupt routine.

If the interrupt is not accepted, the CPU directly executes the instruction following the last instruction

executed before entering the Timer mode.

In case the voltage regulator was manually set to Low Power mode during Timer mode (by setting the

SMCR:LMPSS bit), the wakeup is delayed by typ. 40µs.

Figure 9.4-2 "Release of Timer Mode by Interrupt" shows the release of a Timer mode when an interrupt

occurs (not NMI).

Interrupt from peripheral function

Set the enable ﬂag

Figure 9.4-3 Release of the Timer Mode by External Reset

Depends on RCE bit

Depends on MCE bit

Depends on PCE bit

Depends on SCE bit

Timer mode release

Figure 9.4-4 Release of Timer Mode by Interrupt

INT occurrence?

(IL smaller than 7)

Interrupt is executed

Reset sequence Execution

Reset cleared

Timer mode is not released

Next instruction is executed

Timer mode is

not released

Timer mode is