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CHAPTER 33 FLASH MEMORY
■
Recommended Flash Timing Settings
Table 33.4-4 shows recommended Flash Memory Timing configurations. The maximum operating
frequency of different timing configurations depends on the core supply voltage. Please refer to CHAPTER
9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT for a description how to
program the core supply voltage.
Table 33.4-4 Recommended settings of MFMTCH, MFMTCL and SFMTCH, SFMTCL
FMTCH,
Permitted frequency range for CLKS1
FMTCL
1.8V operation
6E3Dh
f
CLKS1
(can be used at any setting,
especially for mode transitions)
6E3Fh
0239h
f
CLKS1
(init val.)
≤ 30 MHz
f
2129h
CLKS1
≤ 50 MHz
f
CLKS1
233Ah
f
CLKS1
4B3Bh
≤ 60 MHz
f
CLKS1
4B3Dh
≤ 30 MHz
f
2128h
CLKS1
20 MHz ≤ f
CLKS1
2308h
≤ 50 MHz
≤ 76 MHz
f
4C09h
CLKS1
20 MHz ≤ f
CLKS1
6B09h
≤ 92 MHz
f
2279h
CLKS1
f
0231h
CLKS1
1*) Maximum values for f
Note:
When changing any clock settings (change of CLKS1 clock source or CLKB divider setting), use a
854
Permitted
*1)
CLKB
divider
1.9V operation
setting
≤ 100 MHz
1 ... 16
≤ 25 MHz
1 ... 16
≤ 32 MHz
f
1 ... 16
CLKS1
≤ 56 MHz
f
CLKS1
1 ... 16
≤ 20 MHz
≤ 64 MHz
f
1 ... 16
CLKS1
≤ 32 MHz
f
2 ... 16
CLKS1
20 MHz ≤ f
CLKS1
≤ 56 MHz
≤ 84 MHz
f
CLKS1
20 MHz ≤ f
CLKS1
≤ 100 MHz
≤ 40 MHz
2 ... 16
≤ 7 MHz
1 ... 16
and f
CLKS1
Resulting CLKB frequency range
1.8V operation
≤ 100 MHz
f
CLKB
(can be used at any setting,
especially for mode transitions)
≤ 25 MHz
f
CLKB
≤ 30 MHz
f
CLKB
≤ 50 MHz
f
CLKB
≤ 20 MHz
f
CLKB
≤ 60 MHz
f
CLKB
≤ 15 MHz
f
CLKB
10 MHz ≤ f
CLKB
2
≤ 25 MHz
≤ 38 MHz
f
2
CLKB
10 MHz ≤ f
CLKB
2
≤ 46 MHz
≤ 20 MHz
f
CLKB
≤ 7 MHz
f
CLKB
must not exceed the limits defined in the Datasheet.
CLKB
*1)
1.9V operation
Synchronous read with 5
wait states
Synchronous read/write
with 7 wait states
Synchronous read with 1
wait state
Synchronous read with 1
≤ 32 MHz
f
CLKB
wait state
Synchronous read with 2
≤ 56 MHz
f
CLKB
wait states
Synchronous read/write
with 2 wait states
Synchronous read with 3
wait states
≤ 64 MHz
f
CLKB
Synchronous read/write
with 5 wait states
Synchronous read with 0
≤ 16 MHz
f
CLKB
wait states
10 MHz ≤ f
Synchronous read with 0
CLKB
≤ 28 MHz
wait states
Synchronous read with 1
≤ 42 MHz
f
CLKB
wait state
10 MHz ≤ f
Synchronous read with 1
CLKB
≤ 50 MHz
wait state
Synchronous read/write
with 1 wait state
Asynchronous read/write
with 1 wait state
Purpose
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