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APPENDIX
■ Chip erase/sector erase command sequence
Figure C-4 Timing diagram for write access (chip erasing/sector erasing)
AQ18
to
7AAAA
AQ0
CE
t
GHWL
OE
WE
t
CS
DQ7
to
DQ0
V
CC
t
VCS
Note:
SA is the sector address at sector erasing. 7AAAA
1022
t
t
AS
AH
75555
7AAAA
H
H
t
WP
t
WPH
t
DH
AA
55
H
H
t
DS
MB96300 Super Series Hardware Manual
7AAAA
75555
H
H
H
80
AA
H
H
(or 6AAAA
) is the address at chip erasing.
H
H
SA*
55
10
/30
H
H
H
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