Table of Contents
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MB96300 Super Series Hardware Manual
Revision
Date
11
2007-04-24
12
2007-05-15
12
2007-06-16
13
2007-08-06
13
2007-09-28
14
2007-11-20
Corrected some drawing in CHAPTER 36 "EXAMPLES OF SERIAL
PROGRAMMING CONNECTION".
Clock Modulator, RTC and Reset chapters updates
SMC update, EDSU2 add-on, corrections in External Bus register description
Overview: corrected address of PRRR9 in figure 1.14-10
Overview: change block diagram to include USB and CLKP3. Super series lineup
table update
clocks: Add CLKP3 information
Clock ouput function: Add CLKP3 information
USB chapter modified.
Overview modified to include CLKP3 clock domain and MB96330 series.
Chapter 10 updated to include some small corrections and improvements of the
regulator control description.
New USB chapters.
Fig 21.4-8 BGR has 15bits not 14 as previously described.
Chapter 10: typos error corrected.
IOPORT chapter: precision added for PSR and PDR regarding the IER settings.
Flash chapter: table 34.4-1: table title corrected in content and layout. Note on
DQ2 bit added. Flash programming example added
Mask-ROM Interface chapter added
Relaod Timer chapter: TIN pulse length corrected
ROM/Flash security chapter modified to include ROM security features. typo
corrections.
USART: correction in SCDE bit description. Cross-reference added. Typos
SMC. typos corrections.
Annex: IOMAP modified to include GPIO18 &19.
Modification
REVISION HISTORY
1031
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