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CHAPTER 10 SOURCE CLOCK TIMERS
Table 10.2-1 Function Description of Each Bit of the RC Clock Timer Control Register (RCTCR)
Bit name
bit 0 -
RCTI0 to RCTI3:
bit 3
RC Clock Timer
Interrupt interval
select bits
bit 4
RCTR:
RC Clock Timer
Reset bit
bit 5
RCTIF:
RC Clock Timer
Interrupt Flag
bit 6
RCTIE:
RC Clock Timer
Interrupt Enable bit
bit 7
Reserved
266
• These bits control the RC clock timer interrupt interval according to the following
table:
bit3
bit2
bit1
bit0
RCTI3
RCTI2
RCTI1
RCTI0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
• These bits are initialized to "0000" by any reset.
• When data is written to these bits, bit 5 (RCTIF) should be cleared at the same time.
• Please note that above calculated times are based on the nominal RC clock frequency.
The actual frequency and interval times however vary. Please see the datasheet for
more details regarding accuracy of the RC clock frequency.
• This bit clears all bits of the RC clock counter.
• Writing "0" clears the RC clock counter.
• Writing "1" has no effect.
• "1" is always read from this bit.
•
This is an interrupt request flag for the RC clock timer.
• This bit is set to "1" for each interval specified with the RCTI[3:0] bits.
• When this bit is set to "1", an interrupt request is issued if the interrupt enable bit
RCTIE is set to "1".
• This bit is cleared by writing "0" and by any reset.
• Writing "1" has no effect.
• "1" is always read by a read-modify-write instruction.
•
This bit is used to enable interval interrupts based on the RC clock timer.
•
Writing "1" to this bit enables interrupts and writing "0" disables interrupts.
• This bit is reset to "0" by any reset.
• Always write "0" to this bit.
• The read value of this bit is undefined.
• Read modify write operations to this register are not affected.
MB96300 Super Series Hardware Manual
Function
RC Clock Timer Interrupt interval
(The corresponding time for the
nominal RC clock frequency of 2MHz
and 100kHz is given in parentheses)
8
0
2
/ CLKRC (approx. 128µs/2.5ms)
9
1
2
/ CLKRC (approx. 256µs/5.1ms)
10
0
2
/ CLKRC (approx. 512µs/10.2ms)
11
1
2
/ CLKRC (approx. 1ms/20.5ms)
12
0
2
/ CLKRC (approx. 2ms/41ms)
13
1
2
/ CLKRC (approx. 4ms/82ms)
14
0
2
/ CLKRC (approx. 8ms/164ms)
15
1
2
/ CLKRC (approx. 16ms/328ms)
16
0
2
/ CLKRC (approx. 32ms/655ms)
17
1
2
/ CLKRC (approx. 65ms/1.3s)
18
0
2
/ CLKRC (approx. 131m/2.6s)
19
1
2
/ CLKRC (approx. 262ms/5.2s)
20
0
2
/ CLKRC (approx. 524ms/10.4s)
21
1
2
/ CLKRC (approx. 1.05s/21s)
22
0
2
/ CLKRC (approx. 2.1s/42s)
23
1
2
/ CLKRC (approx. 4.2s/84s)
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