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CHAPTER 6 CLOCKS
Table 6.2-6 Function Description of Each Bit of the Clock Input and LVD Control Register (CILCR)
Bit name
bit 8 -
LVL0 to LVL3:
bit 11
Low Voltage
Detector Level
Select bits
bit 12
FCI
bit 13 -
Reserved
bit 15
168
• These bits control the analog threshold level for the Low Voltage Detector (LVD):
LVL3
LVL2
LVL1
LVL0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
• These bits are initialized to "0000" by each reset.
• The Low Voltage Detector circuit will issue a reset request when this function is
enabled and the external supply voltage drops below the selected threshold value.
* Note: For the allowed settings and the analog threshold level, please refer to the
datasheet. For more details refer to CHAPTER 8 RESETS AND STARTUP
• This bit is initialized to "0" by each reset.
• This bit selects the oscillation or Fast Clock Input mode of the Main Oscillator.
FCI
Fast Clock Input Control
0
Oscillation mode
1
Fast External Clock Input mode
• This bit must be set to "0" when connecting an oscillator (crystal/resonator) to the
Main Oscillator Pin X0 and X1. It is also possible to connect an external clock with
low frequency to the oscillator X0/X1 pins in this mode.
• For inputting an external clock with higher frequency, this bit must be set to "1"
before the device is switched to external (main) clock.
• The frequency ranges for both settings are described in the datasheet.
• This feature is not available on all devices. See datasheet for more details.
• Always write "110" to these bits.
• The read value of these bits is undefined.
• Read modify write operations to this register are not affected.
Function
Low voltage detector level
Level 0 *
Level 1 *
Level 2 *
Level 3 *
Level 4 *
Level 5 *
Level 6 *
Level 7 *
Level 8 *
Level 9 *
Level 10 *
Level 11 *
Level 12 *
Level 13 *
Level 14 *
Level 15 *
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